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Date:   Thu, 8 Jul 2021 15:06:18 +0300
From:   Dan Carpenter <dan.carpenter@oracle.com>
To:     kbuild@lists.01.org, Anup Patel <anup.patel@wdc.com>
Cc:     lkp@intel.com, kbuild-all@lists.01.org,
        linux-kernel@vger.kernel.org
Subject: [avpatel:riscv_aia_v1 9/18] drivers/irqchip/irq-aclint-swi.c:262
 aclint_swi_init() warn: 'base' not released on lines: 257.
Message-ID: <202107080927.vpWBnLoc-lkp@intel.com>
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tree:   https://github.com/avpatel/linux.git riscv_aia_v1
head:   e4b6f153340e5471c82603f7b08226ba6e2c6249
commit: 5fc4912d191fc3f4c620e76d500ce19e136d54bf [9/18] irqchip: Add ACLINT software interrupt driver
config: riscv-randconfig-m031-20210707 (attached as .config)
compiler: riscv64-linux-gcc (GCC) 9.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/irqchip/irq-aclint-swi.c:262 aclint_swi_init() warn: 'base' not released on lines: 257.

vim +/base +262 drivers/irqchip/irq-aclint-swi.c

5fc4912d191fc3 Anup Patel 2021-05-13  189  static int __init aclint_swi_init(struct device_node *node,
5fc4912d191fc3 Anup Patel 2021-05-13  190  				  struct device_node *parent)
5fc4912d191fc3 Anup Patel 2021-05-13  191  {
5fc4912d191fc3 Anup Patel 2021-05-13  192  	int rc;
5fc4912d191fc3 Anup Patel 2021-05-13  193  	void __iomem *base;
5fc4912d191fc3 Anup Patel 2021-05-13  194  	struct aclint_swi *swi;
5fc4912d191fc3 Anup Patel 2021-05-13  195  	u32 i, nr_irqs, nr_cpus = 0;
5fc4912d191fc3 Anup Patel 2021-05-13  196  
5fc4912d191fc3 Anup Patel 2021-05-13  197  	/* Map the registers */
5fc4912d191fc3 Anup Patel 2021-05-13  198  	base = of_iomap(node, 0);
                                                ^^^^^^^^^^^^^^^^^^^^^^^^^

5fc4912d191fc3 Anup Patel 2021-05-13  199  	if (!base) {
5fc4912d191fc3 Anup Patel 2021-05-13  200  		pr_err("%pOFP: could not map registers\n", node);
5fc4912d191fc3 Anup Patel 2021-05-13  201  		return -ENODEV;
5fc4912d191fc3 Anup Patel 2021-05-13  202  	}
5fc4912d191fc3 Anup Patel 2021-05-13  203  
5fc4912d191fc3 Anup Patel 2021-05-13  204  	/* Iterarte over each target CPU connected with this ACLINT */
5fc4912d191fc3 Anup Patel 2021-05-13  205  	nr_irqs = of_irq_count(node);
5fc4912d191fc3 Anup Patel 2021-05-13  206  	for (i = 0; i < nr_irqs; i++) {
5fc4912d191fc3 Anup Patel 2021-05-13  207  		struct of_phandle_args parent;
5fc4912d191fc3 Anup Patel 2021-05-13  208  		int cpu, hartid;
5fc4912d191fc3 Anup Patel 2021-05-13  209  
5fc4912d191fc3 Anup Patel 2021-05-13  210  		if (of_irq_parse_one(node, i, &parent)) {
5fc4912d191fc3 Anup Patel 2021-05-13  211  			pr_err("%pOFP: failed to parse irq %d.\n",
5fc4912d191fc3 Anup Patel 2021-05-13  212  			       node, i);
5fc4912d191fc3 Anup Patel 2021-05-13  213  			continue;
5fc4912d191fc3 Anup Patel 2021-05-13  214  		}
5fc4912d191fc3 Anup Patel 2021-05-13  215  
5fc4912d191fc3 Anup Patel 2021-05-13  216  		if (parent.args[0] != RV_IRQ_SOFT) {
5fc4912d191fc3 Anup Patel 2021-05-13  217  			pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
5fc4912d191fc3 Anup Patel 2021-05-13  218  			       node, i, parent.args[0]);
5fc4912d191fc3 Anup Patel 2021-05-13  219  			continue;
5fc4912d191fc3 Anup Patel 2021-05-13  220  		}
5fc4912d191fc3 Anup Patel 2021-05-13  221  
5fc4912d191fc3 Anup Patel 2021-05-13  222  		hartid = riscv_of_parent_hartid(parent.np);
5fc4912d191fc3 Anup Patel 2021-05-13  223  		if (hartid < 0) {
5fc4912d191fc3 Anup Patel 2021-05-13  224  			pr_warn("failed to parse hart ID for irq %d.\n", i);
5fc4912d191fc3 Anup Patel 2021-05-13  225  			continue;
5fc4912d191fc3 Anup Patel 2021-05-13  226  		}
5fc4912d191fc3 Anup Patel 2021-05-13  227  
5fc4912d191fc3 Anup Patel 2021-05-13  228  		cpu = riscv_hartid_to_cpuid(hartid);
5fc4912d191fc3 Anup Patel 2021-05-13  229  		if (cpu < 0) {
5fc4912d191fc3 Anup Patel 2021-05-13  230  			pr_warn("Invalid cpuid for irq %d\n", i);
5fc4912d191fc3 Anup Patel 2021-05-13  231  			continue;
5fc4912d191fc3 Anup Patel 2021-05-13  232  		}
5fc4912d191fc3 Anup Patel 2021-05-13  233  
5fc4912d191fc3 Anup Patel 2021-05-13  234  		/* Find parent domain and register chained handler */
5fc4912d191fc3 Anup Patel 2021-05-13  235  		if (!aclint_swi_parent_irq && irq_find_host(parent.np)) {
5fc4912d191fc3 Anup Patel 2021-05-13  236  			aclint_swi_parent_irq = irq_of_parse_and_map(node, i);
5fc4912d191fc3 Anup Patel 2021-05-13  237  			if (aclint_swi_parent_irq) {
5fc4912d191fc3 Anup Patel 2021-05-13  238  				irq_set_chained_handler(aclint_swi_parent_irq,
5fc4912d191fc3 Anup Patel 2021-05-13  239  							aclint_swi_handle_irq);
5fc4912d191fc3 Anup Patel 2021-05-13  240  				cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
5fc4912d191fc3 Anup Patel 2021-05-13  241  					"irqchip/riscv/aclint-swi:starting",
5fc4912d191fc3 Anup Patel 2021-05-13  242  					aclint_swi_starting_cpu,
5fc4912d191fc3 Anup Patel 2021-05-13  243  					aclint_swi_dying_cpu);
5fc4912d191fc3 Anup Patel 2021-05-13  244  			}
5fc4912d191fc3 Anup Patel 2021-05-13  245  		}
5fc4912d191fc3 Anup Patel 2021-05-13  246  
5fc4912d191fc3 Anup Patel 2021-05-13  247  		swi = per_cpu_ptr(&aclint_swis, cpu);
5fc4912d191fc3 Anup Patel 2021-05-13  248  		swi->sip_reg = base + i * sizeof(u32);
5fc4912d191fc3 Anup Patel 2021-05-13  249  		writel(0, swi->sip_reg);
5fc4912d191fc3 Anup Patel 2021-05-13  250  
5fc4912d191fc3 Anup Patel 2021-05-13  251  		nr_cpus++;
5fc4912d191fc3 Anup Patel 2021-05-13  252  	}
5fc4912d191fc3 Anup Patel 2021-05-13  253  
5fc4912d191fc3 Anup Patel 2021-05-13  254  	/* Create the IPI domain for ACLINT SWI device */
5fc4912d191fc3 Anup Patel 2021-05-13  255  	rc = aclint_swi_domain_init(node);
5fc4912d191fc3 Anup Patel 2021-05-13  256  	if (rc)
5fc4912d191fc3 Anup Patel 2021-05-13  257  		return rc;

This code doesn't do any cleanup.

5fc4912d191fc3 Anup Patel 2021-05-13  258  
5fc4912d191fc3 Anup Patel 2021-05-13  259  	/* Announce the ACLINT SWI device */
5fc4912d191fc3 Anup Patel 2021-05-13  260  	pr_info("%pOFP: providing IPIs for %d CPUs\n", node, nr_cpus);
5fc4912d191fc3 Anup Patel 2021-05-13  261  
5fc4912d191fc3 Anup Patel 2021-05-13 @262  	return 0;
5fc4912d191fc3 Anup Patel 2021-05-13  263  }

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