Received: by 2002:a05:6a10:f3d0:0:0:0:0 with SMTP id a16csp116035pxv; Thu, 8 Jul 2021 16:36:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz4nkvnJzFem6GsNTIaUUrZMqwIW8DEpSIo7lGKwVZNO956hFk0dP4YniVGBQQVlvcff0VO X-Received: by 2002:a92:de45:: with SMTP id e5mr24488747ilr.157.1625787410817; Thu, 08 Jul 2021 16:36:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625787410; cv=none; d=google.com; s=arc-20160816; b=Eym+nd+U75gnqqxXw4090D5VRdeMvNGJKNy6D+ZC8mDgr0xeqWEgrdFRAj7DZ9BLm5 sbZfAcenmHKcjPhcGewXrT/xUd3faGlBoQPT5oqbhc3z9hdHVmco/+lLD/LzR9iGSMCZ Y3MHyecvx5KbajQFrz8H7IbF8zRoDaAv81pddOYODoUEvRWKdHYBmuWkgnp7lh4nTyeU 746WpT4nXsgzNQEeWISdWxEpL2SsGdnSzI5TXRmin1u2P3tQ8HNnUAjG9sIIoZa/l3hi Arqip407hmMU9hbKutJD9fChSHBsXW1GcXpgphgfA1HPQoclXoSiJdcp1eSt8+5dWbQ0 BtiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:user-agent:references:message-id :in-reply-to:subject:cc:to:from:date; bh=l41vt65+Zx0O8NlkL+XPiVHPChMKU8zXFsI6vfJrvA8=; b=V+QTdflM8ii5zTSZPiWVuK6PLpUI8OyYJIzmplbImqq+Z8rMBPh4gU8kii6lMjQE7a 2V0foLHxwTbjLQ4cVgi5crOc+gOLV9c6xuQWm3UE9+uoBlzu822Jaoa+aYfh+gjwyxzr l+3LrwNh13xixO2yf4nQtWKAuEV3CvITabwySg9ou1JmPMHPAlTOdPF72TVxC8nrX+ua D6/vPqaIvklqwyx7Bg8WuK0GvQl8bncSlIEmt2lAMGslxwMVsZekyKSLhXdgxq9d7m1H YXunG7haEMqnzFM5xLtlw5evu34RCTbG23FBF9rqsSbrqMTb+sq6EaPMEArlz486BM2/ ePPQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n12si3975058iob.27.2021.07.08.16.36.39; Thu, 08 Jul 2021 16:36:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229600AbhGHXic (ORCPT + 99 others); Thu, 8 Jul 2021 19:38:32 -0400 Received: from angie.orcam.me.uk ([78.133.224.34]:60560 "EHLO angie.orcam.me.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229491AbhGHXib (ORCPT ); Thu, 8 Jul 2021 19:38:31 -0400 Received: by angie.orcam.me.uk (Postfix, from userid 500) id 46F0192009C; Fri, 9 Jul 2021 01:35:47 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by angie.orcam.me.uk (Postfix) with ESMTP id 403EF92009B; Fri, 9 Jul 2021 01:35:47 +0200 (CEST) Date: Fri, 9 Jul 2021 01:35:47 +0200 (CEST) From: "Maciej W. Rozycki" To: Nikolai Zhubr cc: Bjorn Helgaas , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Arnd Bergmann , x86@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] x86/PCI: Handle PIRQ routing tables with no router device given In-Reply-To: <60E77EBF.2020605@gmail.com> Message-ID: References: <60E726E2.2050104@gmail.com> <60E77EBF.2020605@gmail.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 9 Jul 2021, Nikolai Zhubr wrote: > > Have you tried contacting Nvidia about your ALI chipset? Back in the day > > I tried to avoid undocumented stuff and Intel was reasonably open about > > most of their chipsets. > > Well, being neither their customer nor a kernel developer, I'm not sure my > request would be considered serious. Anyway, probably I'll give it a try a bit > later when I have an opportunity to dismount this board for more comfortable > testing. It never hurts asking. At worst you'll be ignored, and at the second worst they'll say nay. They may have lost it too. > I was also going to try to modify its BIOS to remove some unwanted > behaviour unrelated to IRQs, and it might happen that I also discover > something about PCI handling along with (It is just 64k size, after all, and I > have a 8086 debugger) Umm, the board may be old enough not to play any tricks with the BIOS, but mind that at reset x86 starts in the flat mode from 0xfffffff0 and the contents of ROM there may not be what you see at 0xf000:0xfff0 later on. I once worked on a project where I had an opportunity to access the BIOS at the reset vector (and poke at CPU registers, run, stop, single-step it, place hardware breakpoints, etc.) using GDB over JTAG with an Intel Atom board. It was an interesting experience, but sadly most x86 hardware does not have the capability let alone a JTAG connector (called XDP or eXtended Debug Port in Intel-speak) to attach a probe to. You may try disassembling the PCI BIOS 2.1 service however. Maciej