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Date:   Sun, 11 Jul 2021 10:09:27 -0700
From:   Colin Foster <colin.foster@in-advantage.com>
To:     Vladimir Oltean <olteanv@gmail.com>
Cc:     andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com,
        davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org,
        claudiu.manoil@nxp.com, alexandre.belloni@bootlin.com,
        UNGLinuxDriver@microchip.com, linux@armlinux.org.uk,
        netdev@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH v2 net-next 7/8] net: dsa: ocelot: felix: add support
 for VSC75XX control over SPI
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On Sat, Jul 10, 2021 at 11:52:05PM +0300, Vladimir Oltean wrote:
> On Sat, Jul 10, 2021 at 12:26:01PM -0700, Colin Foster wrote:
> > +static const struct felix_info ocelot_spi_info = {
> > +	.target_io_res			= vsc7512_target_io_res,
> > +	.port_io_res			= vsc7512_port_io_res,
> > +	.regfields			= vsc7512_regfields,
> > +	.map				= vsc7512_regmap,
> > +	.ops				= &vsc7512_ops,
> > +	.stats_layout			= vsc7512_stats_layout,
> > +	.num_stats			= ARRAY_SIZE(vsc7512_stats_layout),
> > +	.vcap				= vsc7512_vcap_props,
> > +	.num_mact_rows			= 1024,
> > +
> > +	/* The 7512 and 7514 both have support for up to 10 ports. The 7511 and
> > +	 * 7513 have support for 4. Due to lack of hardware to test and
> > +	 * validate external phys, this is currently limited to 4 ports.
> > +	 * Expanding this to 10 for the 7512 and 7514 and defining the
> > +	 * appropriate phy-handle values in the device tree should be possible.
> > +	 */
> > +	.num_ports			= 4,
> 
> Ouch, this was probably not a good move.
> felix_setup() -> felix_init_structs sets ocelot->num_phys_ports based on
> this value.
> If you search for ocelot->num_phys_ports in ocelot and in felix, it is
> widely used to denote "the index of the CPU port module within the
> analyzer block", since the CPU port module's number is equal to the
> number of the last physical port + 1. If VSC7512 has 10 ports, then the
> CPU port module is port 10, and if you set num_ports to 4 you will cause
> the driver to misbehave.

Yes, this is part of my concern with the CPU / NPI module mentioned
before. In my hardware, I'd have port 0 plugged to the external CPU. In
Ocelot it is the internal bus, and in Felix it is the NPI. In this SPI
design, does the driver lose significant functionality by not having
access to those ports?

In my test setup (and our expected production) we'd have port 0
connected to the external chip, and ports 1-3 exposed. Does Ocelot need
to be modified to allow a parameter for the CPU port?

And obviously I'd imagine this would want to be done in such a way that
it doesn't break existing device trees...

> 
> > +	.num_tx_queues			= OCELOT_NUM_TC,
> > +	.mdio_bus_alloc			= felix_mdio_bus_alloc,
> > +	.mdio_bus_free			= felix_mdio_bus_free,
> > +	.phylink_validate		= vsc7512_phylink_validate,
> > +	.prevalidate_phy_mode		= vsc7512_prevalidate_phy_mode,
> > +	.port_setup_tc			= vsc7512_port_setup_tc,
> > +	.init_regmap			= vsc7512_regmap_init,
> > +};
> 
> > +	/* Not sure about this */
> > +	ocelot->num_flooding_pgids = 1;
> 
> Why are you not sure? It's the same as ocelot.

Sorry - missed removing that comment... Removed.