Date: Fri, 17 Nov 2006 04:29:22 -0800
From: Stephane Eranian <eranian@hpl.hp.com>
To: Andi Kleen <ak@suse.de>
Cc: Jeremy Fitzhardinge <jeremy@goop.org>, linux-kernel@vger.kernel.org,
       akpm@osdl.org
Subject: Re: [PATCH] i386 add Intel PEBS and BTS cpufeature bits and detection
Message-ID: <20061117122922.GE19907@frankl.hpl.hp.com>
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On Fri, Nov 17, 2006 at 10:22:20AM +0100, Andi Kleen wrote:
> > The former
> > stores from/to information into MSRs and is very small (4 branches). 
> 
> P4 since Prescott has 16
> 
Yes. I was talking about Core 2 

> > On recent processors LBR and BTS can be constrained by priv level.
> 
> Doesn't help for kernel debugging.
> 
Well, if you set if for kernel level only, you do not capture user level
branches. This may happen if you crash soon after you've entered the kernel
and you have a small buffer.

-- 
-Stephane
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