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To:     Yang Weijiang <weijiang.yang@intel.com>,
        Jim Mattson <jmattson@google.com>
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 <20210712095305.GE12162@intel.com>
From:   Like Xu <like.xu.linux@gmail.com>
Subject: Re: [PATCH v5 06/13] KVM: x86/vmx: Save/Restore host MSR_ARCH_LBR_CTL
 state
Message-ID: <d73eb316-4e09-a924-5f60-e3778db91df4@gmail.com>
Date:   Mon, 12 Jul 2021 18:19:10 +0800
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On 12/7/2021 5:53 pm, Yang Weijiang wrote:
> On Fri, Jul 09, 2021 at 04:41:30PM -0700, Jim Mattson wrote:
>> On Fri, Jul 9, 2021 at 3:54 PM Jim Mattson <jmattson@google.com> wrote:
>>>
>>> On Fri, Jul 9, 2021 at 2:51 AM Yang Weijiang <weijiang.yang@intel.com> wrote:
>>>>
>>>> If host is using MSR_ARCH_LBR_CTL then save it before vm-entry
>>>> and reload it after vm-exit.
>>>
>>> I don't see anything being done here "before VM-entry" or "after
>>> VM-exit." This code seems to be invoked on vcpu_load and vcpu_put.
>>>
>>> In any case, I don't see why this one MSR is special. It seems that if
>>> the host is using the architectural LBR MSRs, then *all* of the host
>>> architectural LBR MSRs have to be saved on vcpu_load and restored on
>>> vcpu_put. Shouldn't  kvm_load_guest_fpu() and kvm_put_guest_fpu() do
>>> that via the calls to kvm_save_current_fpu(vcpu->arch.user_fpu) and
>>> restore_fpregs_from_fpstate(&vcpu->arch.user_fpu->state)?
>>
>> It does seem like there is something special about IA32_LBR_DEPTH, though...
>>
>> Section 7.3.1 of the Intel® Architecture Instruction Set Extensions
>> and Future Features Programming Reference
>> says, "IA32_LBR_DEPTH is saved by XSAVES, but it is not written by
>> XRSTORS in any circumstance." It seems like that would require some
>> special handling if the host depth and the guest depth do not match.
> In our vPMU design, guest depth is alway kept the same as that of host,
> so this won't be a problem. But I'll double check the code again, thanks!

KVM only exposes the host's depth value to the user space
so the guest can only use the same depth as the host.

A further reason is that the host perf driver currently
does not support different threads using different depths.