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Date:   Mon, 12 Jul 2021 18:54:31 +0800
From:   Leo Yan <leo.yan@linaro.org>
To:     Suzuki K Poulose <suzuki.poulose@arm.com>
Cc:     Arnaldo Carvalho de Melo <acme@kernel.org>,
        Adrian Hunter <adrian.hunter@intel.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@redhat.com>,
        Namhyung Kim <namhyung@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Borislav Petkov <bp@alien8.de>, x86@kernel.org,
        "H. Peter Anvin" <hpa@zytor.com>,
        Mathieu Poirier <mathieu.poirier@linaro.org>,
        Mike Leach <mike.leach@linaro.org>,
        linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
        coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 02/11] coresight: tmc-etr: Add barrier after updating
 AUX ring buffer
Message-ID: <20210712105431.GA704210@leoy-ThinkPad-X240s>
References: <20210711104105.505728-1-leo.yan@linaro.org>
 <20210711104105.505728-3-leo.yan@linaro.org>
 <f9734d69-b1f5-825c-f152-705626f4b256@arm.com>
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In-Reply-To: <f9734d69-b1f5-825c-f152-705626f4b256@arm.com>
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Hi Suzuki,

On Mon, Jul 12, 2021 at 11:40:12AM +0100, Suzuki Kuruppassery Poulose wrote:
> On 11/07/2021 11:40, Leo Yan wrote:
> > Since a memory barrier is required between AUX trace data store and
> > aux_head store, and the AUX trace data is filled with memcpy(), it's
> > sufficient to use smp_wmb() so can ensure the trace data is visible
> > prior to updating aux_head.
> > 
> > Signed-off-by: Leo Yan <leo.yan@linaro.org>
> > ---
> >   drivers/hwtracing/coresight/coresight-tmc-etr.c | 8 ++++++++
> >   1 file changed, 8 insertions(+)
> > 
> > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> > index acdb59e0e661..713205db15a1 100644
> > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> > @@ -1563,6 +1563,14 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
> >   	 */
> >   	if (etr_perf->snapshot)
> >   		handle->head += size;
> > +
> > +	/*
> > +	 * It requires the ordering between the AUX trace data and aux_head
> > +	 * store, below smp_wmb() ensures the AUX trace data is visible prior
> > +	 * to updating aux_head.
> > +	 */
> 
> Please could we reword this a bit, something like :
> 
> 	/*
> 	 * Ensure that the AUX trace data is visible before the aux_head
> 	 * is updated via perf_aux_output_end(), as expected by the
> 	 * perf ring buffer.
> 	 */

Will refine with this in next spin.  Thanks for review!

> > +	smp_wmb();
> > +
> 
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>