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[23.128.96.18]) by mx.google.com with ESMTP id gb8si22623001ejc.486.2021.07.12.10.48.28; Mon, 12 Jul 2021 10:48:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b="q+5j/qHZ"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235745AbhGLRsL (ORCPT + 99 others); Mon, 12 Jul 2021 13:48:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234728AbhGLRsL (ORCPT ); Mon, 12 Jul 2021 13:48:11 -0400 Received: from mail-ot1-x334.google.com (mail-ot1-x334.google.com [IPv6:2607:f8b0:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A8B5C0613E5 for ; Mon, 12 Jul 2021 10:45:22 -0700 (PDT) Received: by mail-ot1-x334.google.com with SMTP id o17-20020a9d76510000b02903eabfc221a9so19761099otl.0 for ; Mon, 12 Jul 2021 10:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=f5dWuORs6KCnd0V1Z5DOk+p+49s/w8Htm+2uXk9ECuc=; b=q+5j/qHZjMMGvYA2NBvrIxVDwWt+AT46/ShbrWHNKFdOuxq3L0jzpZmkdg97loiATk 5L8DoPhlG/Eloi/M7j57lKkemqfPZ1b300qAcU/vMF0/eMtjYATHWk56GJJxoVhDNU/s MeimQ3vooWBA5HGIUCANcpinA1PS+vE/08aBy7vG7fVVE+7YtzHXjpJXhXbNi8nP5i5p R5B2ZoKQULtypz7PHQ/eZ0Cjw+ArP8qkxLCtdn4buddle6EusHrtRBlNr0IwmaaNJ9rk NsNN1jYATcm3M2veD5v/domkVIcGrvaSbpDGiMUWM9WNg6A33Zt/C5kFL7MCXhBVC6mu qJ4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=f5dWuORs6KCnd0V1Z5DOk+p+49s/w8Htm+2uXk9ECuc=; b=Y2babp+8VaKDzsFutmxGH9qc3WjaAY8u8WVkTD0s01GxHceYPqlcnPfBx9cH/uXEcW +IhtZwx22sz5thMITFUwAI3raidSVwEg1StD9KKuNyTnYN3NxHfXPv5VLuuCPYWFyV4b TfrgdSa+kd+9Ufd0Cc658JhwW1V2EDJjqascAlTyKyHdzOP7/DxLuNEr6DpvTFKleKSC VGG0ve+c44tj2O2PGnSRRrY0ihTGF7nyRI8/TT0pfFogDHWoYX5qNxqGBKKr10coO3jy WMXsoF1a4KsMo83ZXCUIjk73t177KdA+zS38yxHDLvryd3bwJHYzkg3CxRj/CAY5lnNx bFVg== X-Gm-Message-State: AOAM530C2K2XxDZ+g80s9R2xZzkVfOwPnsfFvnXP7ceAiXCV04InZLCk N9cGtRKhMUTNh7oZQkY6f9C/R4IYllQsjJfciDtM/g== X-Received: by 2002:a9d:550e:: with SMTP id l14mr130156oth.241.1626111921557; Mon, 12 Jul 2021 10:45:21 -0700 (PDT) MIME-Version: 1.0 References: <1625825111-6604-1-git-send-email-weijiang.yang@intel.com> <1625825111-6604-7-git-send-email-weijiang.yang@intel.com> <20210712095305.GE12162@intel.com> In-Reply-To: From: Jim Mattson Date: Mon, 12 Jul 2021 10:45:10 -0700 Message-ID: Subject: Re: [PATCH v5 06/13] KVM: x86/vmx: Save/Restore host MSR_ARCH_LBR_CTL state To: Like Xu Cc: Yang Weijiang , pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com, wei.w.wang@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, "kan.liang@linux.intel.com" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jul 12, 2021 at 10:20 AM Jim Mattson wrote: > > On Mon, Jul 12, 2021 at 3:19 AM Like Xu wrote: > > > > On 12/7/2021 5:53 pm, Yang Weijiang wrote: > > > On Fri, Jul 09, 2021 at 04:41:30PM -0700, Jim Mattson wrote: > > >> On Fri, Jul 9, 2021 at 3:54 PM Jim Mattson wro= te: > > >>> > > >>> On Fri, Jul 9, 2021 at 2:51 AM Yang Weijiang wrote: > > >>>> > > >>>> If host is using MSR_ARCH_LBR_CTL then save it before vm-entry > > >>>> and reload it after vm-exit. > > >>> > > >>> I don't see anything being done here "before VM-entry" or "after > > >>> VM-exit." This code seems to be invoked on vcpu_load and vcpu_put. > > >>> > > >>> In any case, I don't see why this one MSR is special. It seems that= if > > >>> the host is using the architectural LBR MSRs, then *all* of the hos= t > > >>> architectural LBR MSRs have to be saved on vcpu_load and restored o= n > > >>> vcpu_put. Shouldn't kvm_load_guest_fpu() and kvm_put_guest_fpu() d= o > > >>> that via the calls to kvm_save_current_fpu(vcpu->arch.user_fpu) and > > >>> restore_fpregs_from_fpstate(&vcpu->arch.user_fpu->state)? > > >> > > >> It does seem like there is something special about IA32_LBR_DEPTH, t= hough... > > >> > > >> Section 7.3.1 of the Intel=C2=AE Architecture Instruction Set Extens= ions > > >> and Future Features Programming Reference > > >> says, "IA32_LBR_DEPTH is saved by XSAVES, but it is not written by > > >> XRSTORS in any circumstance." It seems like that would require some > > >> special handling if the host depth and the guest depth do not match. > > > In our vPMU design, guest depth is alway kept the same as that of hos= t, > > > so this won't be a problem. But I'll double check the code again, tha= nks! > > > > KVM only exposes the host's depth value to the user space > > so the guest can only use the same depth as the host. > > The allowed depth supplied by KVM_GET_SUPPORTED_CPUID isn't enforced, > though, is it? Also, doesn't this end up being a major constraint on future platforms? Every host that this vCPU will ever run on will have to use the same LBR depth as the host on which it was started.