Received: by 2002:a05:6a10:f3d0:0:0:0:0 with SMTP id a16csp3245893pxv; Mon, 12 Jul 2021 12:45:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyES81V5xN7Iy/PHmKleThYjH6hoeSOf0MVhNHwnXH63OeXJ8EL9SJDSXzN/MCBtil9Iiy7 X-Received: by 2002:a05:6e02:f05:: with SMTP id x5mr344046ilj.268.1626119118026; Mon, 12 Jul 2021 12:45:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626119118; cv=none; d=google.com; s=arc-20160816; b=ViAKTFBd2QxQll4kPHmvGYP9U89KzWv3g+IqPs2u8iN3uvu4SP+qqgEvB9C8GXusut /goT45BLNsVgz22odjE8RNr/c0BcumAMzuuEzRJ5Ufqbga2e6U35e/HJDFiHpC4R32zW G4+0fTeEIwnWvhYVr7UKT4SVGbhsqBEblFgw6JcPRnoRt0h1DP6VNqpSIuReshRWpzZk cfzXHQJmv7MsSNDnl31LmH8Dpx8yn1qt7VuNaRCZ+yGxGU6ol3C+dWnNx/argXTiPtiq W6mlzH2kwOLWchIB+L3jwA20RLWbBl/Rbbz979pX1DKZnlciobvcra5/10TS15LSVtL8 qTIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from; bh=llnnWwIwppiTY6WbRPO3oANktVhnDZpMwv7FFam2/Zg=; b=c0ErVlREoWhy/QWFjYhJRcsx3DWDk+F56whbPtv31xueuRSC4p2ra0kPPxKCWVUH18 +ZRxppmr5kxOHUdu9Zahs1Wy1ZbNi7H9+zFw9Befi0gGbA1cLpxyTnO3QIEUi3xU9dy1 KL3rTDB4qSfZBT7NdyZtyZejG1/Lmo4GXdkYVyxDiwDzXrByWw+SH2DWS7KJpkAZi7WY alv0Bp3fHEh1S4kbtJ10Du2LbhubZXKEikGhXw7r4WhEQZXVhOi7VK6nvIhE/Yp9vKsN 7t90HIYspa+yckebUWMpACqdTk5qj02F7GE6g+V1WgRAzcPPmp9hNKlZZn5esVJ4ctvs YL7g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y5si19832069ily.81.2021.07.12.12.45.05; Mon, 12 Jul 2021 12:45:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236414AbhGLTrY (ORCPT + 99 others); Mon, 12 Jul 2021 15:47:24 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:61964 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230199AbhGLTrX (ORCPT ); Mon, 12 Jul 2021 15:47:23 -0400 X-IronPort-AV: E=Sophos;i="5.84,234,1620658800"; d="scan'208";a="87354838" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Jul 2021 04:44:33 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5FE5840E011B; Tue, 13 Jul 2021 04:44:30 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Rob Herring , Linus Walleij , Magnus Damm , Michael Turquette , Stephen Boyd Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 0/5] pin and gpio controller driver for Renesas RZ/G2L Date: Mon, 12 Jul 2021 20:44:17 +0100 Message-Id: <20210712194422.12405-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi All, This patch series adds pin and gpio controller driver for Renesas RZ/G2L SoC. RZ/G2L has a simple pin and GPIO controller combined similar to RZ/A2. This patch series applies on top of https://git.kernel.org/pub/scm/linux/ kernel/git/geert/renesas-drivers.git/log/?h=topic/rzg2l-update-clock-defs-v4 Cheers, Prabhakar Changes for v2: * Added support for per pin pinmux support * Added support for pins to set configs * Dropped pfc-r9a07g044.c/h * Fixed review comments pointed by Geert * Included clock/reset changes * Included DTS/I changes Lad Prabhakar (5): dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add DT bindings for RZ/G2L pinctrl pinctrl: renesas: Add RZ/G2L pin and gpio controller driver drivers: clk: renesas: r9a07g044-cpg: Add GPIO clock and reset entries arm64: dts: renesas: r9a07g044: Add pinctrl node arm64: dts: renesas: rzg2l-smarc: Add scif0 pins .../pinctrl/renesas,rzg2l-pinctrl.yaml | 155 +++ arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 13 + arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 10 + drivers/clk/renesas/r9a07g044-cpg.c | 5 + drivers/pinctrl/renesas/Kconfig | 11 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 1196 +++++++++++++++++ include/dt-bindings/pinctrl/rzg2l-pinctrl.h | 23 + 8 files changed, 1414 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml create mode 100644 drivers/pinctrl/renesas/pinctrl-rzg2l.c create mode 100644 include/dt-bindings/pinctrl/rzg2l-pinctrl.h base-commit: 06c1e6911a7a76b446e4b00fc8bad5d8465932f8 -- 2.17.1