Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Tue, 13 Jul 2021 09:55:08 +0100
From:   Sudeep Holla <sudeep.holla@arm.com>
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     "Lad, Prabhakar" <prabhakar.csengg@gmail.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Sudeep Holla <sudeep.holla@arm.com>,
        Rob Herring <robh+dt@kernel.org>,
        Magnus Damm <magnus.damm@gmail.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH] arm64: dts: renesas: r9a07g044: Add missing GICv3 node
 properties
Message-ID: <20210713085508.nq6473icf5gt3nm5@bogus>
References: <20210611152108.6785-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <CAMuHMdWJQESFmhV+c-QmivXCWPx21QcB-HSzjxf8KsXh_DAvfw@mail.gmail.com>
 <CAMuHMdXG9H_mOtA_a9t0K8BVaR4p0DcWgNeL0786YvybV2Hqgw@mail.gmail.com>
 <CA+V-a8tk6uCeRwmiTh=Ds+8DYVUqCYs64nX_9ksDXXdSd-rxNA@mail.gmail.com>
 <CAMuHMdUg5v3qsFQsg783nC=o_BL3pL6YqqQphGQHHOaCeakj5Q@mail.gmail.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
Content-Transfer-Encoding: 8bit
In-Reply-To: <CAMuHMdUg5v3qsFQsg783nC=o_BL3pL6YqqQphGQHHOaCeakj5Q@mail.gmail.com>
Precedence: bulk

On Tue, Jul 13, 2021 at 10:30:36AM +0200, Geert Uytterhoeven wrote:
> Hi Prabhakar,
> 
> On Tue, Jul 13, 2021 at 10:22 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Tue, Jul 13, 2021 at 9:08 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Mon, Jun 14, 2021 at 2:48 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > On Fri, Jun 11, 2021 at 5:21 PM Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > > Add the below missing properties into GIC node,
> > > > > - clocks
> > > > > - clock-names
> > > > > - power-domains
> > > > > - resets
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > >
> > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > >
> > > > Queueing pending on[1].
> > > >
> > > > > [1] https://lore.kernel.org/linux-devicetree/
> > > > >     20210609155108.16590-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> > >
> > > The dependency has been accepted, but this patch needs a respin
> > > for the changed clocks.
> > >
> > Thank you for pointing this out. wrt resets the GIC has two signals
> > (which I learnt lately when the dependency path was accepted). Earlier
> > discussion in irc with Sudeep pointed out that there wouldn't be any
> > use case of having GIC resets in DTSI, so either we drop the resets
> > property in DT binding doc or correct it.
> >
> > Let me know your thoughts on this and how we proceed further.
>
> DT Rule #1: DT describes hardware not software policy.
>

Completely agreed, no disagreement ????.

> And a possible use case: the RT CPU core may want to reset the AP GIC.
>

I didn't want to add new bindings without details on the implementation
to avoid possible issues with backward compatibility as this was not
thought through completely and correctly before it was added.

OK, now let us discuss your use-case: *RT CPU wants to reset AP GIC*

1. Will it just reset AP GIC or will it request the AP reset as a whole ?
   I am not sure if we can handle former, if you think otherwise what is
   the reset notification mechanism ?

2. Will that bypass secure world/PSCI ? Again more details on this would
   be helpful to visualise the entire use-case end-to-end better.

By GIC reset, I am assuming it will be complete GIC reset including it's
CPU interface.

I don't think we can reset GIC without actual CPU reset. Even if we get
some notification magically to the CPU that its GIC alone needs to be
reset, it needs to safely higher exceptions to get its GIC CPU interface
reprogrammed to correct (saved) values before OS can reprogram the NS
world values. All these seems overall complicated and may be unnecessary.

--
Regards,
Sudeep