Received: by 2002:a05:6a10:f3d0:0:0:0:0 with SMTP id a16csp3882113pxv; Tue, 13 Jul 2021 06:07:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxfsrrTO3wQyolAcrl+24LIW75TO/88bbaJc4AwWw3nZ8NZ91zkcuvhrHmqiR4qZTVkf14s X-Received: by 2002:a02:3781:: with SMTP id r123mr3978700jar.26.1626181639582; Tue, 13 Jul 2021 06:07:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626181639; cv=none; d=google.com; s=arc-20160816; b=iRqx+vf7ryLCFOMz/QSQGq4poBm5+aTKqIhN1olq7ilHC/kyMwjvRcmz8r13xCg7im MZdKdkU6hlLEBeujjanzLqhYSYZKGYfBeg9zKs9c4aKS3fjxNSPtqZucLKp7yDZ/ZAG8 IWc55ZeSt8Zz5iK9YBWFgVA7YO3YvXtDpjgusbwIdHARn4vyQK/ZzJKDRcQAdaMO5B7W VATjofDR8p6GXNTcRCZL6CJ3h7ftrwrDtQS1zb851c78Iyo1SCu20ljhgN1VylWG6aSX CoBkfyOKMDomhyUcAe7mOA1PDqkFDfBOIqmR+Idcu+E8TwSMQBQn2oOQSafFuYR5eJK9 blnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bvwRGkTgaRouJsbI7TnwpzPPO9mZ++9PZ3NrR5V4NMM=; b=bqSr4Q48qP9jQHRJBgjpwtZSO8n+1naMs8gvVyjwA/5efnjKkbJlY31qq/yqoIy8Ln X31ZaZapjHa2JNYa8fC5KuIJW/qiiqEx/qWMW8wjAle40vnM9UNJOrOWqUXI/oos4H6X irCgoRS8+nW74EoMVx5ilpN78EksQTft7asyGVnXwdQqcsst7XiuZFWMPAkwgQMrderB YvhemVBcThGelsjwD+advz2kX2R/cf2lCJfLqi+oT2taM4V5EA80j2Yr1XepTKJ8eECQ b0i+3j+eKs33TEBLE/fAsVtFRH+8X/MTUG9LIbkGg5y9cWs+bGkZy1MAVbKRCQWrbyoz NQcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=X3pj8Evr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z12si22506233iow.36.2021.07.13.06.06.59; Tue, 13 Jul 2021 06:07:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=X3pj8Evr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236587AbhGMNJF (ORCPT + 99 others); Tue, 13 Jul 2021 09:09:05 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43680 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236222AbhGMNJC (ORCPT ); Tue, 13 Jul 2021 09:09:02 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16DD5sT0010356; Tue, 13 Jul 2021 08:05:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626181554; bh=bvwRGkTgaRouJsbI7TnwpzPPO9mZ++9PZ3NrR5V4NMM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=X3pj8Evrk4NbnJBOPXFVmUuKbr61oAOtGUoHjMj7xgT5g6wDcmwR8lzFcBWPPHGC+ Q9zGcvTLe2xxKsTC929ftJbrKrk8lF8hvpYybHucl0G2Z64lF1Q6oPQGaSBm51tk2h UxEN6N22OevJeF4FVKJFE2/Fifde8K/JQKr/0V+A= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16DD5sNr085828 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Jul 2021 08:05:54 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 13 Jul 2021 08:05:54 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 13 Jul 2021 08:05:54 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16DD5daC109825; Tue, 13 Jul 2021 08:05:50 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Boris Brezillon , , , CC: Apurva Nandan , Pratyush Yadav Subject: [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Date: Tue, 13 Jul 2021 13:05:27 +0000 Message-ID: <20210713130538.646-3-a-nandan@ti.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20210713130538.646-1-a-nandan@ti.com> References: <20210713130538.646-1-a-nandan@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Unlike Dual and Quad SPI modes flashes, Octal DTR SPI NAND flashes require all instructions to be made in 8D-8D-8D protocol when the flash is in Octal DTR mode. Hence, storing the current SPI IO mode becomes necessary for correctly generating non-array access operations. Store the current SPI IO mode in the spinand struct using a reg_proto enum. This would act as a flag, denoting that the core should use the given SPI protocol for non-page access operations. Also provide basic macros for extracting buswidth and dtr mode information from the spinand_proto enum. Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 2 ++ include/linux/mtd/spinand.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 446ba8d43fbc..a4f25649e293 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1153,6 +1153,7 @@ static void spinand_mtd_resume(struct mtd_info *mtd) struct spinand_device *spinand = mtd_to_spinand(mtd); int ret; + spinand->reg_proto = SPINAND_SINGLE_STR; ret = spinand_reset_op(spinand); if (ret) return; @@ -1179,6 +1180,7 @@ static int spinand_init(struct spinand_device *spinand) if (!spinand->scratchbuf) return -ENOMEM; + spinand->reg_proto = SPINAND_SINGLE_STR; ret = spinand_detect(spinand); if (ret) goto err_free_bufs; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 6988956b8492..f6093cd98d7b 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -140,6 +140,31 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(len, buf, 4)) +#define SPINAND_PROTO_BUSWIDTH_MASK GENMASK(6, 0) +#define SPINAND_PROTO_DTR_BIT BIT(7) + +#define SPINAND_PROTO_STR(__buswidth) \ + ((u8)(((__buswidth) - 1) & SPINAND_PROTO_BUSWIDTH_MASK)) +#define SPINAND_PROTO_DTR(__buswidth) \ + (SPINAND_PROTO_DTR_BIT | SPINAND_PROTO_STR(__buswidth)) + +#define SPINAND_PROTO_BUSWIDTH(__proto) \ + ((u8)(((__proto) & SPINAND_PROTO_BUSWIDTH_MASK) + 1)) +#define SPINAND_PROTO_IS_DTR(__proto) (!!((__proto) & SPINAND_PROTO_DTR_BIT)) + +/** + * enum spinand_proto - List allowable SPI protocol variants for read reg, + * write reg, blk erase, write enable/disable, page read + * and program exec operations. + */ +enum spinand_proto { + SPINAND_SINGLE_STR = SPINAND_PROTO_STR(1), + SPINAND_DUAL_STR = SPINAND_PROTO_STR(2), + SPINAND_QUAD_STR = SPINAND_PROTO_STR(4), + SPINAND_OCTAL_STR = SPINAND_PROTO_STR(8), + SPINAND_OCTAL_DTR = SPINAND_PROTO_DTR(8), +}; + /** * Standard SPI NAND flash commands */ @@ -407,6 +432,9 @@ struct spinand_dirmap { * this die. Only required if your chip exposes several dies * @cur_target: currently selected target/die * @eccinfo: on-die ECC information + * @reg_proto: select a variant of SPI IO protocol (single, quad, octal or + * octal DTR) for read_reg/write_reg/erase operations. Update on + * successful transition into a different SPI IO protocol. * @cfg_cache: config register cache. One entry per die * @databuf: bounce buffer for data * @oobbuf: bounce buffer for OOB data @@ -438,6 +466,8 @@ struct spinand_device { struct spinand_ecc_info eccinfo; + enum spinand_proto reg_proto; + u8 *cfg_cache; u8 *databuf; u8 *oobbuf; -- 2.17.1