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Date:   Tue, 13 Jul 2021 19:25:50 +0100
From:   Mark Brown <broonie@kernel.org>
To:     Apurva Nandan <a-nandan@ti.com>
Cc:     linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
        Pratyush Yadav <p.yadav@ti.com>,
        Vignesh Raghavendra <vigneshr@ti.com>
Subject: Re: [PATCH 1/2] spi: cadence-quadspi: Disable Auto-HW polling
Message-ID: <20210713182550.GG4098@sirena.org.uk>
References: <20210713125743.1540-1-a-nandan@ti.com>
 <20210713125743.1540-2-a-nandan@ti.com>
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On Tue, Jul 13, 2021 at 12:57:41PM +0000, Apurva Nandan wrote:

> cadence-quadspi controller doesn't allow an address phase when
> auto-polling the busy bit on the status register. Unlike SPI NOR
> flashes, SPI NAND flashes do require the address of status register
> when polling the busy bit using the read register operation. As
> Auto-HW polling is enabled by default, cadence-quadspi returns a
> timeout for every write operation after an indefinite amount of
> polling on SPI NAND flashes.

> Disable Auto-HW polling completely as the spi-nor core, spinand core,
> etc. take care of polling the busy bit on their own.

Would it not be better to only disable this on NAND rather than
disabling it completely?

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