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Date:   Tue, 13 Jul 2021 20:22:57 -0600
From:   Rob Herring <robh@kernel.org>
To:     Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Cc:     Bjorn Helgaas <helgaas@kernel.org>, linuxarm@huawei.com,
        mauro.chehab@huawei.com, Manivannan Sadhasivam <mani@kernel.org>,
        Kishon Vijay Abraham I <kishon@ti.com>,
        Vinod Koul <vkoul@kernel.org>, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH v5 1/8] dt-bindings: phy: Add bindings for HiKey 960 PCIe
 PHY
Message-ID: <20210714022257.GA1320622@robh.at.kernel.org>
References: <cover.1626157454.git.mchehab+huawei@kernel.org>
 <390e7fc0cd6fa4217f5d67c74f12ea101fab3f6d.1626157454.git.mchehab+huawei@kernel.org>
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On Tue, Jul 13, 2021 at 08:28:34AM +0200, Mauro Carvalho Chehab wrote:
> Document the bindings for HiKey 960 (hi3660) PCIe PHY
> interface, supported via the pcie-kirin driver.
> 
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> ---
>  .../phy/hisilicon,phy-hi3660-pcie.yaml        | 82 +++++++++++++++++++
>  1 file changed, 82 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
> new file mode 100644
> index 000000000000..81c93e76cef4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3660-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: HiSilicon Kirin960 PCIe PHY
> +
> +maintainers:
> +  - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> +
> +description: |+
> +  Bindings for PCIe PHY on HiSilicon Kirin 960.
> +
> +properties:
> +  compatible:
> +    const: hisilicon,hi960-pcie-phy
> +
> +  "#phy-cells":
> +    const: 0
> +
> +  reg:
> +    maxItems: 1
> +    description: PHY Control registers
> +
> +  reg-names:
> +    const: phy

You don't really need reg-names with only 1.

> +
> +  clocks:
> +    items:
> +      - description: PCIe PHY clock
> +      - description: PCIe AUX clock
> +      - description: PCIe APB PHY clock
> +      - description: PCIe APB SYS clock
> +      - description: PCIe ACLK clock
> +
> +  clock-names:
> +    items:
> +      - const: pcie_phy_ref
> +      - const: pcie_aux
> +      - const: pcie_apb_phy
> +      - const: pcie_apb_sys
> +      - const: pcie_aclk

'pcie_' is redundant. Drop.

> +
> +  reset-gpios:
> +    description: PCI PERST reset GPIO

maxItems: 1

Though this belongs in the PCIE node.

> +
> +required:
> +  - "#phy-cells"
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names
> +  - reset-gpios
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/hi3660-clock.h>
> +
> +    bus {
> +      #address-cells = <2>;
> +      #size-cells = <2>;
> +      pcie_phy: pcie-phy@f3f2000 {
> +        compatible = "hisilicon,hi960-pcie-phy";
> +        reg = <0x0 0xf3f20000 0x0 0x40000>;
> +        reg-names = "phy";
> +        clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
> +                 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
> +                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
> +                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
> +                 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
> +        clock-names = "pcie_phy_ref", "pcie_aux",
> +                 "pcie_apb_phy", "pcie_apb_sys",
> +                 "pcie_aclk";
> +        reset-gpios = <&gpio11 1 0 >;
> +        #phy-cells = <0>;
> +      };
> +    };
> +...
> -- 
> 2.31.1
> 
>