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}; + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , /* Physical Secure */ -- 2.17.1