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Subject: Re: [PATCH 1/2] spi: cadence-quadspi: Disable Auto-HW polling
To:     Mark Brown <broonie@kernel.org>
CC:     <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        Pratyush Yadav <p.yadav@ti.com>,
        Vignesh Raghavendra <vigneshr@ti.com>
References: <20210713125743.1540-1-a-nandan@ti.com>
 <20210713125743.1540-2-a-nandan@ti.com> <20210713182550.GG4098@sirena.org.uk>
From:   "Nandan, Apurva" <a-nandan@ti.com>
Message-ID: <f1947183-81d2-3519-d25f-71d93f59e434@ti.com>
Date:   Wed, 14 Jul 2021 18:52:12 +0530
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On 13-Jul-21 11:55 PM, Mark Brown wrote:
> On Tue, Jul 13, 2021 at 12:57:41PM +0000, Apurva Nandan wrote:
> 
>> cadence-quadspi controller doesn't allow an address phase when
>> auto-polling the busy bit on the status register. Unlike SPI NOR
>> flashes, SPI NAND flashes do require the address of status register
>> when polling the busy bit using the read register operation. As
>> Auto-HW polling is enabled by default, cadence-quadspi returns a
>> timeout for every write operation after an indefinite amount of
>> polling on SPI NAND flashes.
> 
>> Disable Auto-HW polling completely as the spi-nor core, spinand core,
>> etc. take care of polling the busy bit on their own.
> 
> Would it not be better to only disable this on NAND rather than
> disabling it completely?
> 

I am not sure how it is possible currently in the controller, could you
please suggest a way? Also, should we have this logic of checking flash
device type in the cadence-quadspi controller? SPI controller should be
generic to all flash cores right?

In my opinion, it shouldn't harm as spi-nor core doesn't depend on HW
polling anyways and auto-HW polling is a minor overhead.

Regards,
Apurva Nandan