Received: by 2002:a05:6a10:f3d0:0:0:0:0 with SMTP id a16csp436446pxv; Wed, 14 Jul 2021 07:23:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzSWnElruKYSfySNg+Ne4nHnWnHK1jG4jYVCd9rw9JHN0Lj3ZTIXA2hN16j2Vr6er6njPDF X-Received: by 2002:a17:906:4f14:: with SMTP id t20mr12329248eju.12.1626272599702; Wed, 14 Jul 2021 07:23:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626272599; cv=none; d=google.com; s=arc-20160816; b=KTJG3rlS+VoHMNzdSGXKvnwyyUCpElPe762ONzGx0aThzxgv6D+33kJLo8bVDrz6FB 9xxFwiFLeO8YEHkXRVzi8eJmwatiVdl6I9keqh4kN9PSbz9XqkN8AyNKjEkKbcM5SWs4 0jbkX1S4Tz3O4bQXmkV/GpBLioSVftFkXDOSE6X5NNLaoAYS/llMI1Anvtn2ubsEZ0ep qa8bnvHX2P3G009hB7G2atvvNmlKR7C+U5ABCRtWQl6XbfsuvxweD2XON200/R2Ufz9I x99uFljHQVa/f4qKt4NKj7hQIi7IZ1fHTi2BSjbxI/Q1sR3H5VfpuFcSJswWzS4hpRCP yEoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:organization:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=QPwHOYxHr0wqhs0Pr81jpQvkvSrMQBdm2C+cP/91Wko=; b=G7WQk+HnULyuG8LHEcod5wMWG0yEpN14io0YM98gXmRAORpCa3UOaWoCJj/YM8i4k3 siRgLNc4v+aRudlptxs6+xLP59FExbyfFCJbJOD8Ah2o5D41lB3QtMukQ2uOC8qLq1mj 6TJBbOKlD+ELvr5lIxurNi39SNkaZISmgT3SDtzYvSPpGEjH3z/B+yCb+X/uBqTphNnh B1aIGYsuEj+Bm3QxBoWXRCJEfhz714r++SdmOZCUGtF7Jw5mM07KcPkMDyrP0O+DJHLV X2+oRSs+dmQ0NZXRLYI8r1j0IG0Y3dJ6x0gMEGyz4RstNj14xYU/5Q1F27BD5E94uqG8 2vWQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w10si3281079ejv.584.2021.07.14.07.22.55; Wed, 14 Jul 2021 07:23:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232268AbhGNOXz (ORCPT + 99 others); Wed, 14 Jul 2021 10:23:55 -0400 Received: from mga14.intel.com ([192.55.52.115]:33729 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232097AbhGNOXx (ORCPT ); Wed, 14 Jul 2021 10:23:53 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10044"; a="210170332" X-IronPort-AV: E=Sophos;i="5.84,239,1620716400"; d="scan'208";a="210170332" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2021 07:21:01 -0700 X-IronPort-AV: E=Sophos;i="5.84,239,1620716400"; d="scan'208";a="413300245" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2021 07:20:58 -0700 Received: from andy by smile with local (Exim 4.94.2) (envelope-from ) id 1m3fkq-00DLq4-QY; Wed, 14 Jul 2021 17:20:52 +0300 Date: Wed, 14 Jul 2021 17:20:52 +0300 From: Andy Shevchenko To: Rob Herring Cc: shruthi.sanil@intel.com, Daniel Lezcano , Thomas Gleixner , "linux-kernel@vger.kernel.org" , devicetree@vger.kernel.org, kris.pan@linux.intel.com, Mark Gross , srikanth.thokala@intel.com, "Raja Subramanian, Lakshmi Bai" , mallikarjunappa.sangannavar@intel.com Subject: Re: [PATCH v4 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer Message-ID: References: <20210628061410.8009-1-shruthi.sanil@intel.com> <20210628061410.8009-2-shruthi.sanil@intel.com> <20210714024756.GA1355219@robh.at.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 14, 2021 at 08:07:44AM -0600, Rob Herring wrote: > On Wed, Jul 14, 2021 at 3:04 AM Andy Shevchenko > wrote: > > On Tue, Jul 13, 2021 at 08:47:56PM -0600, Rob Herring wrote: > > > On Mon, Jun 28, 2021 at 11:44:09AM +0530, shruthi.sanil@intel.com wrote: > > > > > > + The parent node represents the common general configuration details and > > > > + the child nodes represents the counter and timers. > > > > > > I don't think all the child nodes are necessary. Are the counters and > > > timers configurable (say on another SoC)? If not, then a single node > > > here would suffice. > > > > If you may notice the children may have different properties that can't be > > known ahead, such as IRQ line. On some platforms it may be this mapping, on > > another it maybe different. > > What I noticed is it's all the same clock and 1 interrupt for each > timer can be just a single 'interrupts' property with 8 entries. This may work. > Is there a platform that's different or that's a hypothetical? Because > hypothetically, every aspect of every IP could change. But we don't > try to parameterize everything in DT. It's a judgement call between > implying things from compatible and explicit DT properties. > > > With all respect for the simplification I think we can't do it here. > > You can. Any data in DT could be in the kernel. It's a question of > balance, not can or can't. Not only, it's also matters of what exactly hardware is: 8 timers or timer with 8 channels. If it's the former one, I prefer to have DT exactly like originally suggested, otherwise I will agree on your proposal. -- With Best Regards, Andy Shevchenko