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[94.29.37.113]) by smtp.googlemail.com with ESMTPSA id s5sm689535ljg.63.2021.07.15.08.36.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Jul 2021 08:36:32 -0700 (PDT) Subject: Re: [PATCH v3 02/12] dt-bindings: phy: tegra20-usb-phy: Document properties needed for OTG mode To: Rob Herring Cc: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org References: <20210704225433.32029-1-digetx@gmail.com> <20210704225433.32029-3-digetx@gmail.com> <20210712154139.GB1980362@robh.at.kernel.org> <8fe56e89-9e1e-f5e2-5a47-242b5b3d085a@gmail.com> <20210714231000.GB3697673@robh.at.kernel.org> From: Dmitry Osipenko Message-ID: <73e1e3a2-c2dd-364b-7829-84e66b114909@gmail.com> Date: Thu, 15 Jul 2021 18:36:31 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210714231000.GB3697673@robh.at.kernel.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 15.07.2021 02:10, Rob Herring пишет: > On Tue, Jul 13, 2021 at 02:33:11AM +0300, Dmitry Osipenko wrote: >> 12.07.2021 18:41, Rob Herring пишет: >>>> + nvidia,pmc: >>>> + $ref: /schemas/types.yaml#/definitions/phandle >>>> + description: >>>> + Phandle to Power Management controller. >>>> + >>> Add a cell to this for the PHY reg offset and then get rid of the index: >>> >>>> + nvidia,phy-instance: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + minimum: 0 >>>> + maximum: 2 >>>> + description: Unique hardware ID. >> >> The instance ID belongs to the USB h/w and not to PMC. It may look like >> I added the ID just to get offsets within PMC, but it's not like that. >> The Tegra documentation explicitly assigns unique IDs to the USB >> controllers and PHYs. Hence this ID should be the property of the PHY >> hardware, IMO. > > It looks like the use is calculating register offsets in a PMC register. > That's quite common and including that with the phandle is the preferred > way to describe it. > > Lots of docs have UART1, UART2, UART3, etc. module numbering. We don't > copy that into DT. Alright. Judging by downstream code, we will need to use that ID only for PMC offsets.