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Date:   Thu, 15 Jul 2021 17:41:42 +0100
From:   Mark Brown <broonie@kernel.org>
To:     Apurva Nandan <a-nandan@ti.com>
Cc:     linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
        Pratyush Yadav <p.yadav@ti.com>,
        Vignesh Raghavendra <vigneshr@ti.com>
Subject: Re: [PATCH 1/2] spi: cadence-quadspi: Disable Auto-HW polling
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On Thu, Jul 15, 2021 at 09:57:51PM +0530, Apurva Nandan wrote:

> Now, whether the poll instruction should have an address phase or not
> depends on the connected flash chip, which the controller wouldn't be
> aware of as it only takes in a spimem op from the flash cores for execution.

...

> More to this, not just address phase but any kind of variation in the
> read register operation would result in polling failure.

That seems like something that should be fixed since it means that no
controller will be able to support a feature like this - it needs to get
enough information passed to it to allow it to poll correctly.

> Any SPI operation that is going underneath the visibility of flash core
> can can problems. I agree offloading the status polling process to
> controller HW is beneficial but on the other hand it restricts the flash
> on having a fixed type of polling operation. This would reduce the
> number of flash devices it will support (out of the box).
> What should be the right way out for this situation?

One idea would be to have something that takes both the operation itself
and the operation that's used to poll for status (with expected result),
the controller can then check the poll operation and either tell the
core it's not supported or go ahead and do the polling.  Or simpler just
a separate poll operation which is fully specified enough.

Not actually looked at the code to see how tasteful that is though...

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