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[188.155.177.222]) by smtp.gmail.com with ESMTPSA id m26sm1274584edf.4.2021.07.16.01.10.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Jul 2021 01:10:27 -0700 (PDT) Subject: Re: [PATCH] usb: dwc2: Skip clock gating on Samsung SoCs To: Marek Szyprowski , linux-usb@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Minas Harutyunyan , Felipe Balbi , Artur Petrosyan , Bartlomiej Zolnierkiewicz References: <20210716050127.4406-1-m.szyprowski@samsung.com> From: Krzysztof Kozlowski Message-ID: Date: Fri, 16 Jul 2021 10:10:26 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210716050127.4406-1-m.szyprowski@samsung.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/07/2021 07:01, Marek Szyprowski wrote: > Commit 0112b7ce68ea ("usb: dwc2: Update dwc2_handle_usb_suspend_intr > function.") changed the way the driver handles power down modes in a such > way that it uses clock gating when no other power down mode is available. > > This however doesn't work well on the DWC2 implementation used on the > Samsung SoCs. When a clock gating is enabled, system hangs. It looks that > the proper clock gating requires some additional glue code in the shared > USB2 PHY and/or Samsung glue code for the DWC2. To restore driver > operation on the Samsung SoCs simply skip enabling clock gating mode > until one finds what is really needed to make it working reliably. > > Fixes: 0112b7ce68ea ("usb: dwc2: Update dwc2_handle_usb_suspend_intr function.") > Signed-off-by: Marek Szyprowski > --- > drivers/usb/dwc2/core.h | 4 ++++ > drivers/usb/dwc2/core_intr.c | 3 ++- > drivers/usb/dwc2/hcd.c | 6 ++++-- > drivers/usb/dwc2/params.c | 1 + > 4 files changed, 11 insertions(+), 3 deletions(-) > Acked-by: Krzysztof Kozlowski Best regards, Krzysztof