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Date:   Fri, 16 Jul 2021 20:57:57 +0800
From:   Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To:     Alex Ghiti <alex@ghiti.fr>
Cc:     Palmer Dabbelt <palmer@dabbelt.com>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        Jisheng Zhang <jszhang@kernel.org>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Arnd Bergmann <arnd@arndb.de>
Subject: Re: [GIT PULL] RISC-V Patches for the 5.14 Merge Window, Part 1
Message-ID: <20210716205758.05620241@xhacker>
In-Reply-To: <cb401208-8774-9653-e780-6e9d4d3a41c0@ghiti.fr>
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        <cb401208-8774-9653-e780-6e9d4d3a41c0@ghiti.fr>
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On Thu, 15 Jul 2021 09:11:14 +0200
Alex Ghiti <alex@ghiti.fr> wrote:

> Hi Palmer,
>=20
> Le 11/07/2021 =C3=A0 20:45, Palmer Dabbelt a =C3=A9crit=C2=A0:
> > On Fri, 09 Jul 2021 12:58:10 PDT (-0700), alex@ghiti.fr wrote: =20
> >>
> >>
> >> Le 9/07/2021 =C3=A0 16:53, Palmer Dabbelt a =C3=A9crit=C2=A0: =20
> >>> The following changes since commit=20
> >>> 8a4102a0cf07cc76a18f373f6b49485258cc6af4:
> >>>
> >>> =C2=A0=C2=A0 riscv: mm: Fix W+X mappings at boot (2021-06-01 21:15:09=
 -0700)
> >>>
> >>> are available in the Git repository at:
> >>>
> >>> =C2=A0=C2=A0 git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linu=
x.git=20
> >>> tags/riscv-for-linus-5.14-mw0
> >>>
> >>> for you to fetch changes up to 1958e5aef5098e28b7d6e6a2972649901ebeca=
ce:
> >>>
> >>> =C2=A0=C2=A0 riscv: xip: Fix duplicate included asm/pgtable.h (2021-0=
7-06=20
> >>> 16:17:40 -0700)
> >>>
> >>> ----------------------------------------------------------------
> >>> RISC-V Patches for the 5.14 Merge Window, Part 1
> >>>
> >>> In addition to We have a handful of new features for 5.14:
> >>>
> >>> * Support for transparent huge pages.
> >>> * Support for generic PCI resources mapping.
> >>> * Support for the mem=3D kernel parameter.
> >>> * Support for KFENCE.
> >>> * A handful of fixes to avoid W+X mappings in the kernel.
> >>> * Support for VMAP_STACK based overflow detection.
> >>> * An optimized copy_{to,from}_user.
> >>> ----------------------------------------------------------------
> >>> There are some Kconfig merge conflicts.=C2=A0 They should be pretty
> >>> straight-forward, but we do have a symbol out of order -- I thought I=
=20
> >>> had a
> >>> script to check for that, but I guess it doesn't work.=C2=A0 I just s=
ent=20
> >>> out a patch
> >>> to fix it up.
> >>>
> >>> diff --cc arch/riscv/Kconfig
> >>> index 3590eb76000e,469a70bd8da6..d36f3c5029fd
> >>> --- a/arch/riscv/Kconfig
> >>> +++ b/arch/riscv/Kconfig
> >>> @@@ -60,12 -61,11 +61,12 @@@ config RISC
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select GENERIC_TIME_=
VSYSCALL if MMU && 64BIT
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HANDLE_DOMAIN=
_IRQ
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_AUD=
ITSYSCALL
> >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_JUMP_LABEL
> >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_JUMP_LABEL_REL=
ATIVE
> >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_JUMP_LABEL if =
!XIP_KERNEL
> >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_JUMP_LABEL_REL=
ATIVE if !XIP_KERNEL
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KAS=
AN if MMU && 64BIT
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KAS=
AN_VMALLOC if MMU && 64BIT
> >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KFENCE if MMU=
 && 64BIT
> >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KGDB
> >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KGDB if !XIP_K=
ERNEL
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_KGD=
B_QXFER_PKT
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_MMA=
P_RND_BITS if MMU
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_SEC=
COMP_FILTER
> >>> @@@ -81,11 -80,9 +82,14 @@@
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_GCC_PLUG=
INS
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_GENERIC_=
VDSO if MMU && 64BIT
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_IRQ_TIME=
_ACCOUNTING
> >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KPROBES
> >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KPROBES_ON_FTRACE
> >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KRETPROBES
> >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KPROBES if !XIP_KER=
NEL
> >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KPROBES_ON_FTRACE i=
f !XIP_KERNEL
> >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_KRETPROBES if !XIP_=
KERNEL
> >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_MOVE_PMD
> >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_MOVE_PUD
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_PCI
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_PERF_EVE=
NTS
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_PERF_REGS
> >>> @@@ -108,7 -104,7 +112,8 @@@
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select SYSCTL_EXCEPT=
ION_TRACE
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select THREAD_INFO_I=
N_TASK
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select UACCESS_MEMCP=
Y if !MMU
> >>> =C2=A0 +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select HAVE_ARCH_TRANSPARENT_H=
UGEPAGE if 64BIT && MMU
> >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select ZONE_DMA32 if 64BIT
> >>>
> >>> =C2=A0=C2=A0 config ARCH_MMAP_RND_BITS_MIN
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 default 18 if 64BIT
> >>> ----------------------------------------------------------------
> >>> Akira Tsukamoto (1):
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv: __asm_copy_to-from_user: =
Optimize unaligned memory=20
> >>> access and pipeline stall
> >>>
> >>> Alexandre Ghiti (6):
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv: Remove CONFIG_PHYS_RAM_BA=
SE_FIXED
> >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv: Simplify xip and !xip ker=
nel address conversion macros =20
> >>
> >> @Palmer: As said in the thread of this patchset multiple times, those 2
> >> patches should not be merged as it assumes that the base DRAM address =
is
> >> always 0x8000_0000 for all rv64 platforms: I don't think it is true,=20
> >> is it? =20
> >=20
> > Sorry, I remember saying something about that but must have missed the=
=20
> > resposeses.=C2=A0 Do you have a pointer to the discussion?=C2=A0 If thi=
s break=20
> > stuff I'm happy to revert it, which can be done post-rc1.=C2=A0 I just =
need=20
> > to see what's actually broken first, because IIUC this was de-facto how=
=20
> > things worked already.
> >  =20
>=20
> Really sorry about my response delay.
>=20
> The thing is that removing CONFIG_PHYS_RAM_BASE_FIXED defines=20
> CONFIG_PHYS_RAM_BASE to 0x8000_0000 for all rv64 chips, but I believe=20
> this is implementation specific: for now, this base address was passed=20
> into the device tree, and here it makes this value static.
>=20
> This issue with my patch was originally pointed by Jisheng, Geert and Arn=
d.
>=20
> If this is not a problem and you have a pointer to a document that=20
> specifies this, I would be very happy to have the link :)
>=20
> Thanks and again sorry about my response delay,
>=20

Hi Alex,

Since the PR has been merged into linux-5.14-rc1, directly reverting seems
not a good idea. IMHO, it's better to send patch(es) against current 5.14-r=
c1
tree. what do you think?

Thanks