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Date:   Fri, 16 Jul 2021 14:53:01 +0000
From:   Wei Liu <wei.liu@kernel.org>
To:     Ani Sinha <ani@anisinha.ca>
Cc:     linux-kernel@vger.kernel.org, anirban.sinha@nokia.com,
        mikelley@microsoft.com, "K. Y. Srinivasan" <kys@microsoft.com>,
        Haiyang Zhang <haiyangz@microsoft.com>,
        Stephen Hemminger <sthemmin@microsoft.com>,
        Wei Liu <wei.liu@kernel.org>, Dexuan Cui <decui@microsoft.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
        linux-hyperv@vger.kernel.org
Subject: Re: [PATCH v2] x86/hyperv: add comment describing
 TSC_INVARIANT_CONTROL MSR setting bit 0
Message-ID: <20210716145301.xsho5zb7cqkgb3zc@liuwe-devbox-debian-v2>
References: <20210716133245.3272672-1-ani@anisinha.ca>
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On Fri, Jul 16, 2021 at 07:02:45PM +0530, Ani Sinha wrote:
> Commit dce7cd62754b5 ("x86/hyperv: Allow guests to enable InvariantTSC")
> added the support for HV_X64_MSR_TSC_INVARIANT_CONTROL. Setting bit 0
> of this synthetic MSR will allow hyper-v guests to report invariant TSC
> CPU feature through CPUID. This comment adds this explanation to the code
> and mentions where the Intel's generic platform init code reads this
> feature bit from CPUID. The comment will help developers understand how
> the two parts of the initialization (hyperV specific and non-hyperV
> specific generic hw init) are related.
> 
> Signed-off-by: Ani Sinha <ani@anisinha.ca>

Applied to hyperv-next. Thanks.