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From:   Apurva Nandan <a-nandan@ti.com>
To:     Mark Brown <broonie@kernel.org>, <linux-spi@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
CC:     Apurva Nandan <a-nandan@ti.com>, Pratyush Yadav <p.yadav@ti.com>,
        Vignesh Raghavendra <vigneshr@ti.com>
Subject: [PATCH v2 0/2] spi: cadence-quadspi: Fix DTR op checks and timeout in SPI NAND write operations
Date:   Fri, 16 Jul 2021 23:25:01 +0000
Message-ID: <20210716232504.182-1-a-nandan@ti.com>
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Hi,
This series proposes fixes for cadence-quadspi controller for the
following issues with SPI NAND flashes:

- Due to auto-HW polling without address phase, the cadence-quadspi
  controller timeouts when performing any write operation on SPI NAND
  flash.

- When checking for DTR spi_mem_op, cadence-quadspi doesn't ignore a
  zero length phase in the SPI instruction, resulting in false negatives.

This series has been tested on TI J721e EVM with the Winbond W35N01JW
flash.

v1 series: https://lore.kernel.org/linux-spi/20210713125743.1540-1-a-nandan@ti.com/

Changes in v2:
- [PATCH v2 1/2]: Same as v1. This patch has been already applied to
  https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
  commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling")

- [PATCH v2 2/2]: Add new comments to explain the DTR check conditions

Apurva Nandan (2):
  spi: cadence-quadspi: Disable Auto-HW polling
  spi: cadence-quadspi: Fix check condition for DTR ops

 drivers/spi/spi-cadence-quadspi.c | 48 ++++++++++++++++++++-----------
 1 file changed, 32 insertions(+), 16 deletions(-)

-- 
2.17.1