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Date:   Sat, 17 Jul 2021 16:56:05 -0700
From:   Moritz Fischer <mdf@kernel.org>
To:     Mark Brown <broonie@kernel.org>
Cc:     Martin =?iso-8859-1?Q?Hundeb=F8ll?= <martin@geanix.com>,
        Wu Hao <hao.wu@intel.com>, Tom Rix <trix@redhat.com>,
        Moritz Fischer <mdf@kernel.org>, Xu Yilun <yilun.xu@intel.com>,
        Jean Delvare <jdelvare@suse.com>,
        Guenter Roeck <linux@roeck-us.net>,
        Martin =?iso-8859-1?Q?Hundeb=F8ll?= <mhu@silicom.dk>,
        linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-hwmon@vger.kernel.org, linux-spi@vger.kernel.org
Subject: Re: [PATCH v5 2/3] spi: spi-altera-dfl: support n5010 feature
 revision
Message-ID: <YPNuFX4ZfwJoOlMk@epycbox.lan>
References: <20210716135441.3235863-1-martin@geanix.com>
 <20210716135441.3235863-3-martin@geanix.com>
 <20210716173335.GC4137@sirena.org.uk>
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On Fri, Jul 16, 2021 at 06:33:35PM +0100, Mark Brown wrote:
> On Fri, Jul 16, 2021 at 03:54:40PM +0200, Martin Hundeb?ll wrote:
> > From: Martin Hundeb?ll <mhu@silicom.dk>
> > 
> > The Max10 BMC on the Silicom n5010 PAC is slightly different than the
> > existing BMCs, so use a dedicated feature revision detect it.
> 
> Acked-by: Mark Brown <broonie@kernel.org>

Mark do you want me to provide a tag for this and the previous commit to
avoid conflicts for other FPGA changes or do you think it's easier to
just pick both of them up through FPGA or SPI tree?

- Moritz