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From:   Lino Sanfilippo <LinoSanfilippo@gmx.de>
To:     Vladimir Oltean <olteanv@gmail.com>
Cc:     Andrew Lunn <andrew@lunn.ch>, woojung.huh@microchip.com,
        UNGLinuxDriver@microchip.com, vivien.didelot@gmail.com,
        f.fainelli@gmail.com, davem@davemloft.net, kuba@kernel.org,
        netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Aw: Re: [PATCH 2/2] net: dsa: tag_ksz: dont let the hardware
 process the layer 4 checksum
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Date:   Mon, 19 Jul 2021 10:20:13 +0200
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Hi,

> Gesendet: Donnerstag, 15. Juli 2021 um 16:36 Uhr
> Von: "Vladimir Oltean" <olteanv@gmail.com>
> An: "Andrew Lunn" <andrew@lunn.ch>
> Cc: "Lino Sanfilippo" <LinoSanfilippo@gmx.de>, woojung.huh@microchip.com=
, UNGLinuxDriver@microchip.com, vivien.didelot@gmail.com, f.fainelli@gmail=
.com, davem@davemloft.net, kuba@kernel.org, netdev@vger.kernel.org, linux-=
kernel@vger.kernel.org
> Betreff: Re: [PATCH 2/2] net: dsa: tag_ksz: dont let the hardware proces=
s the layer 4 checksum
>
> On Thu, Jul 15, 2021 at 03:08:53PM +0200, Andrew Lunn wrote:
> > > - If we inherit NETIF_F_HW_CSUM from the master for tail taggers, it=
 is
> > >   actively detrimential to keep this feature enabled, as proven my L=
ino.
> > >   As for header taggers, I fail to see how this would be helpful, si=
nce
> > >   the DSA master would always fail to see the real IP header (it has
> > >   been pushed to the right by the DSA tag), and therefore, the DSA
> > >   master offload would be effectively bypassed.
> >
> > The Marvell MACs know about DSA and should be able to perform hardware
> > checksumming. It is a long time since i looked at how this works, but
> > i think there is a field in the descriptor which gets set with the
> > offset to the IP header, so it work for DSA as well as EDSA.
> >
> > I _think_ Broadcom MACs also know about Broadcom tags and can do the
> > right thing.
> >
> > So we need to be a bit careful here to prevent performance regressions
> > for same vendor MAC+Switch combinations.
>
> Tell me more (show me some code). Do Marvell Ethernet controllers which
> support TX checksumming with Marvell switches do different things
> depending on whether DSA or EDSA is used? Because we can currently
> toggle between DSA and EDSA at runtime.
>
> This new information means we can only accept Lino's patch 2/2 as-is for
> the "net" tree, otherwise we will introduce regressions one way or
> another. It will only be a partial fix for the particular case of KSZ
> switches which probably have no DSA master counterpart to support TX
> checksumming.
>

Should I then resend the series with patch 1 handling the NETIF_F_SG and
NETIF_F_FRAGLIST flags (i.e. deleting them if tailroom is needed) in
dsa_slave_setup_tagger() as you suggested and patch 2 as it is?

Regards,
Lino