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References: <20210714211805.22350-1-richard.laing@alliedtelesis.co.nz>
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From:   Loic Poulain <loic.poulain@linaro.org>
Date:   Mon, 19 Jul 2021 12:11:26 +0200
Message-ID: <CAMZdPi-1E5pieVwt_XFF-+PML-cX05nM=PdD0pApD_ym5k_uMQ@mail.gmail.com>
Subject: Re: [PATCH] bus: mhi: pci-generic: configurable network interface MRU
To:     richard.laing@alliedtelesis.co.nz
Cc:     David Miller <davem@davemloft.net>,
        Network Development <netdev@vger.kernel.org>,
        open list <linux-kernel@vger.kernel.org>
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Hi Richard,

On Wed, 14 Jul 2021 at 23:18, <richard.laing@alliedtelesis.co.nz> wrote:
>
> From: Richard Laing <richard.laing@alliedtelesis.co.nz>
>
> The MRU value used by the MHI MBIM network interface affects
> the throughput performance of the interface. Different modem
> models use different default MRU sizes based on their bandwidth
> capabilities. Large values generally result in higher throughput
> for larger packet sizes.


For my interest do you have some numbers here highlighting improvement?

> In addition if the MRU used by the MHI device is larger than that
> specified in the MHI net device the data is fragmented and needs
> to be re-assembled which generates a (single) warning message about
> the fragmented packets. Setting the MRU on both ends avoids the
> extra processing to re-assemble the packets.


Re-assembly is quite free since it's about chaining buffers (no copy
or re-alloc).

>
>
> This patch allows the documented MRU for a modem to be automatically
> set as the MHI net device MRU avoiding fragmentation and improving
> throughput performance.


I would be interested in some numbers (throughput, CPU usage...) since
I've not been able to test that at very high throughput for MBIM. The
default MRU has been set so that MHI packets fit into 4K pages, for
faster allocation. As you said, that causes more MHI transfers but
there is Interrupt Coalescing at hardware level, which mitigates
overhead.

Regards,
Loic