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From:   David Abdurachmanov <david.abdurachmanov@gmail.com>
Date:   Mon, 19 Jul 2021 20:12:37 +0300
Message-ID: <CAEn-LTqq8+B4HRV_1aHSrrRRwd9Xvpd3mBg0fUixtHb_4-4u6w@mail.gmail.com>
Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive
 FU740-C000 SoC
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Yash Shah <yash.shah@sifive.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Rob Herring <robh+dt@kernel.org>,
        Thierry Reding <thierry.reding@gmail.com>,
        Palmer Dabbelt <palmer@dabbelt.com>
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On Fri, Jul 16, 2021 at 3:51 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Yash,
>
> On Tue, Dec 8, 2020 at 5:57 AM Yash Shah <yash.shah@sifive.com> wrote:
> > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
> > around the SiFIve U7 Core Complex and a TileLink interconnect.
> >
> > This file is expected to grow as more device drivers are added to the
> > kernel.
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
>
> Thanks for your patch, which became commit 57985788158a5a6b ("riscv:
> dts: add initial support for the SiFive FU740-C000 SoC").
>
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > @@ -0,0 +1,293 @@
>
> > +       cpus {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +               cpu0: cpu@0 {
> > +                       compatible = "sifive,bullet0", "riscv";
>
> I'm wondering why you're using
>
>     compatible = "sifive,bullet0", "riscv";
>
> According to your own commit 75e6d7248efccc2b ("dt-bindings: riscv:
> Update DT binding docs to support SiFive FU740 SoC"), it should be
>
>     compatible = "sifive,u74-mc", "riscv";
>
> instead.

I plan to send out new DT for the Rev3A and Rev3B (the final board
customers can buy) boards.
This is already fixed in meta-sifive.

In general bullet here is micro architecture, but it's less
descriptive in /proc/cpuinfo.

>
> Likewise, the older arch/riscv/boot/dts/sifive/fu540-c000.dtsi is using
>
>     compatible = "sifive,e51", "sifive,rocket0", "riscv";
>
> and
>
>     compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
>
> but according to the DT bindings the rocket part should not be present.
>
> Is there any specific reason for that?
> Should the DT bindings and/or the DTS files be fixed?
>
> Thanks!
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
>
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