Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Subject: Re: [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node
To:     Nishanth Menon <nm@ti.com>
CC:     <kristo@kernel.org>,
        Device Tree Mailing List <devicetree@vger.kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Linux ARM Mailing List <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
References: <20210719085402.28569-1-lokeshvutla@ti.com>
 <20210719085402.28569-4-lokeshvutla@ti.com>
 <20210719152326.op7ii76nvk5sve2a@fringe>
From:   Lokesh Vutla <lokeshvutla@ti.com>
Message-ID: <d5d614f4-339b-59a1-bd29-6c78d09f2d89@ti.com>
Date:   Tue, 20 Jul 2021 10:46:40 +0530
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101
 Thunderbird/68.10.0
MIME-Version: 1.0
In-Reply-To: <20210719152326.op7ii76nvk5sve2a@fringe>
Content-Type: text/plain; charset="utf-8"
Content-Language: en-US
Content-Transfer-Encoding: 7bit
Precedence: bulk


On 19/07/21 8:53 pm, Nishanth Menon wrote:
> On 14:24-20210719, Lokesh Vutla wrote:
>> ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a
>> signal connected to Pin 1 of J3. Add support for adding this pinmux so
>> that pwm can be observed on pin 1 of Header J3
>>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
>> ---
>>  arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
>> index d3aa2901e6fd..eb0d10e6e787 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
>> @@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
>>  			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
>>  		>;
>>  	};
>> +
>> +	main_ecap0_pins_default: main-ecap0-pins-default {
>> +		pinctrl-single,pins = <
>> +			AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>> +		>;
>> +	};
>>  };
>>  
>>  &mcu_uart0 {
>> @@ -453,3 +459,9 @@ &pcie0_rc {
>>  &pcie0_ep {
>>  	status = "disabled";
>>  };
>> +
>> +&ecap0 {
>> +	/* PWM is available on Pin 1 of header J3 */
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&main_ecap0_pins_default>;
>> +};
>> -- 
>> 2.30.0
>>
> 
> 
> Do the other ecap and pwm nodes need to be disabled since they may not
> be pinned out?

Sure, Ill mark other ecap and epwm nodes as disabled. After looking at
schematics, epwm4 and 5 is pinned out on RPI header. But the header will most
likely be used for other use-cases. Shall I mark epwm4 and epwm5 disabled as
well with a comment with this information?

Thanks and regards,
Lokesh

>