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Date:   Tue, 20 Jul 2021 12:24:39 +0530
From:   Prasad Malisetty <pmaliset@codeaurora.org>
To:     Stephen Boyd <swboyd@chromium.org>
Cc:     agross@kernel.org, bhelgaas@google.com, bjorn.andersson@linaro.org,
        lorenzo.pieralisi@arm.com, robh+dt@kernel.org,
        svarbanov@mm-sol.com, devicetree@vger.kernel.org,
        linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org,
        linux-kernel@vger.kernel.org, dianders@chromium.org,
        mka@chromium.org, vbadigan@codeaurora.org, sallenki@codeaurora.org
Subject: Re: [PATCH v4 2/4] arm64: dts: qcom: sc7280: Add PCIe and PHY related
 nodes
In-Reply-To: <CAE-0n506Phfr=HBYgg+KDHaDAN7+GqmJSeviv7mpY=x973yd5A@mail.gmail.com>
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On 2021-07-17 01:01, Stephen Boyd wrote:
> Quoting Prasad Malisetty (2021-07-16 06:58:45)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index a8c274a..06baf88 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -15,6 +15,7 @@
>>  #include <dt-bindings/reset/qcom,sdm845-pdc.h>
>>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>>  #include <dt-bindings/thermal/thermal.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> 
>>  / {
>>         interrupt-parent = <&intc>;
>> @@ -546,6 +547,118 @@
>>                         #power-domain-cells = <1>;
> 
> Is this the gpucc node? At address 3d90000? Please sort the nodes based
> on their address, so this would be 1c08000 which comes before gpucc and
> some others in this file.
> 
sure, I will move it accordingly.
>>                 };
>> 
>> +               pcie1: pci@1c08000 {
>> +                       compatible = "qcom,pcie-sc7280", 
>> "qcom,pcie-sm8250", "snps,dw-pcie";
>> +                       reg = <0 0x01c08000 0 0x3000>,
>> +                             <0 0x40000000 0 0xf1d>,
>> +                             <0 0x40000f20 0 0xa8>,
>> +                             <0 0x40001000 0 0x1000>,
>> +                             <0 0x40100000 0 0x100000>;
>> +