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[23.128.96.18]) by mx.google.com with ESMTP id m19si17563874ejn.748.2021.07.20.06.16.20; Tue, 20 Jul 2021 06:16:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238454AbhGTMcj (ORCPT + 99 others); Tue, 20 Jul 2021 08:32:39 -0400 Received: from mail-io1-f54.google.com ([209.85.166.54]:37477 "EHLO mail-io1-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234942AbhGTMb3 (ORCPT ); Tue, 20 Jul 2021 08:31:29 -0400 Received: by mail-io1-f54.google.com with SMTP id r18so12756553iot.4; Tue, 20 Jul 2021 06:12:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:in-reply-to:references:subject:date :message-id; bh=3uaiIA266oYzcSw5ViiNhUOcSHy5KGVbduxtAyiJ2M4=; b=l1tWZ6ch5T16FJKcP2NGOCubyZTcfKqqfdJDGVnBsyotEw90fIynBrJ9xn5fzxbOpA yWRWtmpL5SwD6k2CdiD6m9mttkJ8kQUDa0cgKIKA1Gky3gRGFR2V0/lAt1RNotzPAFfn /LI7C2OAxH3BRipPJ8lh1j0tfHGx3B1Gy8T6ssQs4A1JtsDz5EWClX59sUxhpJSOCDzZ p98rRykAT+4Neqe+Ig8YFUAAvNWkStsHXO6cMFMY0d4C+cDch1pO6/FPeC4eBUiPSrby l15leE+jz0rr4MTou9E9+OH4IOm5JXCvPX+s7yjCGu+1TsCJbprExfg6dCsTzW0oB17K rVcA== X-Gm-Message-State: AOAM532k4YaPYlcaJhwmwt4cb0oZHrMc7gLn95Dao1B8BfA8P5ph7JYd OHfOTYad8jbUIuBLuleUQQ== X-Received: by 2002:a02:2382:: with SMTP id u124mr26150014jau.138.1626786720858; Tue, 20 Jul 2021 06:12:00 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.248]) by smtp.gmail.com with ESMTPSA id h6sm11993036iop.40.2021.07.20.06.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 06:12:00 -0700 (PDT) Received: (nullmailer pid 4121601 invoked by uid 1000); Tue, 20 Jul 2021 13:11:58 -0000 From: Rob Herring To: Sean Anderson Cc: Lee Jones , Alvaro Gamez , linux-kernel@vger.kernel.org, =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-arm-kernel@lists.infradead.org, Thierry Reding , devicetree@vger.kernel.org, michal.simek@xilinx.com, linux-pwm@vger.kernel.org In-Reply-To: <20210719221322.3723009-1-sean.anderson@seco.com> References: <20210719221322.3723009-1-sean.anderson@seco.com> Subject: Re: [PATCH v5 1/3] dt-bindings: pwm: Add Xilinx AXI Timer Date: Tue, 20 Jul 2021 07:11:58 -0600 Message-Id: <1626786718.716987.4121600.nullmailer@robh.at.kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 19 Jul 2021 18:13:20 -0400, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a > "soft" block, so it has some parameters which would not be configurable in > most hardware. This binding is usually automatically generated by Xilinx's > tools, so the names and values of some properties should be kept as they > are, if possible. In addition, this binding is already in the kernel at > arch/microblaze/boot/dts/system.dts, and in user software such as QEMU. > > The existing driver uses the clock-frequency property, or alternatively the > /cpus/timebase-frequency property as its frequency input. Because these > properties are deprecated, they have not been included with this schema. > All new bindings should use the clocks/clock-names properties to specify > the parent clock. > > Because we need to init timer devices so early in boot, we determine if we > should use the PWM driver or the clocksource/clockevent driver by the > presence/absence, respectively, of #pwm-cells. Because both counters are > used by the PWM, there is no need for a separate property specifying which > counters are to be used for the PWM. > > Signed-off-by: Sean Anderson > --- > > Changes in v5: > - Update commit message to reflect revisions > - Fix indentation lint > - Add example for timer binding > - Remove xlnx,axi-timer-2.0 compatible string > - Move schema into the timer directory > > Changes in v4: > - Remove references to generate polarity so this can get merged > - Predicate PWM driver on the presence of #pwm-cells > - Make some properties optional for clocksource drivers > > Changes in v3: > - Mark all boolean-as-int properties as deprecated > - Add xlnx,pwm and xlnx,gen?-active-low properties. > - Make newer replacement properties mutually-exclusive with what they > replace > - Add an example with non-deprecated properties only. > > Changes in v2: > - Use 32-bit addresses for example binding > > .../bindings/timer/xlnx,xps-timer.yaml | 91 +++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml: $id: relative path/filename doesn't match actual path or filename expected: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml# \ndoc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1507329 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.