Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp4728450pxv; Tue, 20 Jul 2021 10:13:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzTxeEbUl6v6ycPsKWtG8k1SRc9v0JsMJFkifAy4bO6sPtn1grdVZcNya/MjTROhYsA83KA X-Received: by 2002:a17:906:8158:: with SMTP id z24mr33975833ejw.359.1626801233408; Tue, 20 Jul 2021 10:13:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626801233; cv=none; d=google.com; s=arc-20160816; b=n8JjS/0bMXeFiWkOvAgzFjzxcEw6cCK/ovFwC9XdHwmWi4L05KJRX+dDPrJmqtZHXU EuwNtGDPVDRUlSkRbfsZAKGizUp9MKgG79OrDYB0+YMK/mQmyZgFhPs4Pt6qdzaO0nXL 4QaWTQQenIK0+KszvMz7TlAaST8tByQM6n/gKhIiC9B7bx0RHFs/N3Kbo5xE9s5a6nUB 40fsBHmmc6fX+u23e8LK73+3ccHYOvJMzQX5zzsLD9eMZPuun4pM2dnjUlg7MiiJokDk he6qe3a/C1TEhBzQX5Lj3ka8GivUqcZaAKvnJ3VenvVQZpAJS2Z8eLxbtn/fwgti0GEd QMsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:content-language :in-reply-to:mime-version:user-agent:date:message-id:from:references :cc:to:subject; bh=vlI9AMz1JasuItioc+3mvRCgiu0J7Tx6y95sxypbv9s=; b=WK24q4o4fpS0qqSSWgquXMFwqbe/JN/1MabUNcx181dFJtcS0owQE8jepTkw8SANIT A+TSyofVXay3ZxAi96ZWR/Q05u2NpaYISBcbrVboQ3qdPVW1l/glZoFyCM4S/HiT3npQ ClK325eGDXNbICkVvDbN/sfKu3q3gxHo9ILbuurCOjwVcOUCXxN0lkUXNSq7HMqmTT8+ nDwcz3NSvdLkt1bd2hFG/YBukfnJURLTcwcA3ty3wri/JHWVhgviJeabXUEi7g5U+ZSp uHPQAaOcYwwah4VaHssKu/XjzRDvBWj76s4lanl0IH4+hbkB40/bu3aXMx7/t65TG0CW 7pUQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x41si23707021edy.469.2021.07.20.10.13.29; Tue, 20 Jul 2021 10:13:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230433AbhGTQaQ (ORCPT + 99 others); Tue, 20 Jul 2021 12:30:16 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:57284 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234988AbhGTQ0z (ORCPT ); Tue, 20 Jul 2021 12:26:55 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id E657D1F43318 Subject: Re: [PATCH v2 6/7] soc: mediatek: mmsys: Add reset controller support To: Philipp Zabel , linux-kernel@vger.kernel.org Cc: chunkuang.hu@kernel.org, hsinyi@chromium.org, kernel@collabora.com, drinkcat@chromium.org, eizan@chromium.org, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, jitao.shi@mediatek.com, linux-arm-kernel@lists.infradead.org References: <20210714101141.2089082-1-enric.balletbo@collabora.com> <20210714121116.v2.6.I15e2419141a69b2e5c7e700c34d92a69df47e04d@changeid> <039151e1f17676a101fb9c0682f5ee9fb8ad502d.camel@pengutronix.de> From: Enric Balletbo i Serra Message-ID: Date: Tue, 20 Jul 2021 19:07:14 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <039151e1f17676a101fb9c0682f5ee9fb8ad502d.camel@pengutronix.de> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Philipp, Thank you to take a look On 20/7/21 12:52, Philipp Zabel wrote: > Hi Enric, > > On Wed, 2021-07-14 at 12:11 +0200, Enric Balletbo i Serra wrote: >> Among other features the mmsys driver should implement a reset >> controller to be able to reset different bits from their space. >> >> Cc: Jitao Shi >> Suggested-by: Chun-Kuang Hu >> Signed-off-by: Enric Balletbo i Serra > > The reset controller driver looks fine, just two questions below. > >> --- >> >> (no changes since v1) >> >> drivers/soc/mediatek/mtk-mmsys.c | 69 ++++++++++++++++++++++++++++++++ >> drivers/soc/mediatek/mtk-mmsys.h | 2 + >> 2 files changed, 71 insertions(+) >> >> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c >> index e681029fe804..6ac4deff0164 100644 >> --- a/drivers/soc/mediatek/mtk-mmsys.c >> +++ b/drivers/soc/mediatek/mtk-mmsys.c > [...] >> @@ -91,6 +95,59 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > [...] >> +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id) >> +{ >> + int ret; >> + >> + ret = mtk_mmsys_reset_assert(rcdev, id); >> + if (ret) >> + return ret; >> + >> + usleep_range(1000, 1100); > > Is this known to be enough for all IP cores that can be reset by this > controller? > This time is copied from the downstream kernel, so, tbh, I am not totally sure is enough or needed. Let me try to reach the Mediatek people for if they can answer this. >> + return mtk_mmsys_reset_deassert(rcdev, id); >> +} >> + >> +static const struct reset_control_ops mtk_mmsys_reset_ops = { >> + .assert = mtk_mmsys_reset_assert, >> + .deassert = mtk_mmsys_reset_deassert, >> + .reset = mtk_mmsys_reset, >> +}; >> + >> static int mtk_mmsys_probe(struct platform_device *pdev) >> { >> struct device *dev = &pdev->dev; >> @@ -111,6 +168,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev) >> return ret; >> } >> >> + spin_lock_init(&mmsys->lock); >> + >> + mmsys->rcdev.owner = THIS_MODULE; >> + mmsys->rcdev.nr_resets = 32; > > Are all bits in the MMSYS_SW0_RST_B register individual reset controls? Yes, all are individual reset controls, mostly related to display but not all (i.e dsi, dpi ...) Thanks, Enric > > regards > Philipp >