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Date:   Tue, 20 Jul 2021 13:30:42 -0500
From:   Bjorn Helgaas <helgaas@kernel.org>
To:     Pali =?iso-8859-1?Q?Roh=E1r?= <pali@kernel.org>
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
        Marek =?iso-8859-1?Q?Beh=FAn?= <kabel@kernel.org>,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [RESEND PATCH 2/3] PCI: aardvark: Fix checking for PIO status
Message-ID: <20210720183042.GA108003@bjorn-Precision-5520>
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On Tue, Jul 20, 2021 at 08:11:55PM +0200, Pali Roh?r wrote:
> On Tuesday 20 July 2021 11:34:51 Bjorn Helgaas wrote:
> > On Tue, Jul 20, 2021 at 04:49:55PM +0200, Pali Roh?r wrote:

> > > So what should pci-aardvark driver in this case do? Return ~0 or re-send
> > > this config read request (and how many times)?
> > 
> > That's a good question.  I don't know what other hardware
> > implementations do, but I doubt they retry forever.  Since the spec
> > doesn't specify a number of retries, I think you can choose to do
> > none and immediately return ~0.
> 
> Ok, so I will change implementation to return ~0 without any retry. This
> is simple and easy implementation. Anyway, it would be nice to know what
> other real-hardware implementations of PCIe controllers are doing.
> 
> PCI_EXP_RTCTL_CRSSVE bit is only part of kernel emulated PCIe Bridge and
> has no real register in aardvark hw.
> 
> So for me it looks like that aardvark's pci_ops.read() should set read
> value to ~0 or 0xffff0001 based on what is stored in kernel emulated
> PCI_EXP_RTCTL_CRSSVE bit. Right?

Yes, that would be my advice.  Of course it's only if we're reading
the Vendor ID *and* PCI_EXP_RTCTL_CRSSVE is set.