Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp5265853pxv; Wed, 21 Jul 2021 01:02:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAzeD7a5OgD1p6HxT2xLL8yzZ6rEj6VWAPU5WZ02WVP7KDI/h/NjpGuI6V2erwQXJJjk7s X-Received: by 2002:a6b:6f11:: with SMTP id k17mr25725616ioc.114.1626854557272; Wed, 21 Jul 2021 01:02:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626854557; cv=none; d=google.com; s=arc-20160816; b=K6vlGtBOb5MT+qJ3KcUzdzbv3Wedwy82FvuTJ3ylVtzk6fmsOTN3PsC6hRBgCam1dJ ds6/j0WEyhjWVrQcuhAFACtobwToIIYP4o8BRbzCjX5OipdT47mFnJ57UsHZvhjDQLOj DyzVGDziv1MiGml2E+YFxfKFchKW2Y3d74fP5fbApR65cRsDX7ZVBrj91UJ0GKfaFALm p2o3Wi63+M4tPo//sSGXZmZlJ0HjKxRy8CgcOrvIahgjKPn/1tJQzm4A+jCUeXjh79/E kSOLFlzlq+c8mMz0lRdH01XlT7dOMTPiPHETZof5XXXOaLsF6zWyD4RFyeMyR3iOGecE EELQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:cc:to:subject :message-id:date:from:in-reply-to:references:mime-version :dkim-signature; bh=i1uzYLmR5eIDsH2uz91oXJvOO8JLzGZfgbFg19OYUOg=; b=X5Hla58EWgLkdO/ALDkGyH8APnIj3JTjoGe8jTVAbtwcauUULgifwEzHmstvf0phN1 ZrVDttQu2/sLZk1k1XjbHgInjJvY831sq77OxmKiankurTc/iN6d7ZEdMAIyZh5oxqDw 3HCI84jGIjK+AY37ej/KxFOVJrurkCdg0MOPd2ufZApKnIg5eyCjg+XFcQrVUOR/pzCP a1qhVbNO540gVwAipczfPYqt5e+d2B53BiXDLPKMTW4qsF1to0m/r9IIHLx7W4KyUxnS /BHbu+LGb4+J7bd2TDmiyZViblRCkMuhtzCGFcQin5V6Fh1mtgo6hw5N40qxk/juqTm3 m3Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ffwll.ch header.s=google header.b=iIIO8uiP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w12si26086744ilv.127.2021.07.21.01.02.25; Wed, 21 Jul 2021 01:02:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ffwll.ch header.s=google header.b=iIIO8uiP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234757AbhGUHU3 (ORCPT + 99 others); Wed, 21 Jul 2021 03:20:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233957AbhGUHS7 (ORCPT ); Wed, 21 Jul 2021 03:18:59 -0400 Received: from mail-ot1-x329.google.com (mail-ot1-x329.google.com [IPv6:2607:f8b0:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EE31C061766 for ; Wed, 21 Jul 2021 00:59:31 -0700 (PDT) Received: by mail-ot1-x329.google.com with SMTP id o72-20020a9d224e0000b02904bb9756274cso1300066ota.6 for ; Wed, 21 Jul 2021 00:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=i1uzYLmR5eIDsH2uz91oXJvOO8JLzGZfgbFg19OYUOg=; b=iIIO8uiPJd8ABtw13Umn0Qzy4qd108xTqg9zeHtryzTqn1f23VsT6sj+Xdy7fw5pB0 JXSSOKWxIHPm+DTThfW4L7RTzyfLxc59rBMx365YGzyk7XQRM47pp7v+T9hNYttlfAKv plx0mOufPHR8h5iNXoImM0LMpyzeJIirrUpPY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=i1uzYLmR5eIDsH2uz91oXJvOO8JLzGZfgbFg19OYUOg=; b=ghqrR9sJHKqy8xF1h2wsWWp0No23ybAKXHHXEWJl+qV6xD6TQsH8KWr1psgOPnzyRP oLbks1Z3L/6RZN958gygxgZnh98fARitmHc5m2R3P3NuDQ8Tt0kcZ6M8rNJz+3jbxtKL WBFgsiNrVcWhNr4L3DQL6ko8p+A+FyYNc146MFw+jFKdcyUL4NbHptKO5ZKJFzWQvqrB P2Bk6qVZzMDO865/Kwtjsv8nipl1vwZ8W0B2UcHvkQSFcIv/xjJZxE/Kq+3KLDJbg63Z 057wca0ZiSY2a/7vsoLZ+F1TjnxYSo0zqunEOqNpDu498uWDmxsEQ/H+yUMLbsq6wx84 p3Zg== X-Gm-Message-State: AOAM530sDLdapdRGZMjN0skLEm/DL/jX1y/HeIu3qudNyf+Cw6rcGATu yYcBQZ1hcen8BhJFpfSBWj+QMg9qqWwEmxHZQRTcmQ== X-Received: by 2002:a9d:6d86:: with SMTP id x6mr11443606otp.188.1626854370953; Wed, 21 Jul 2021 00:59:30 -0700 (PDT) MIME-Version: 1.0 References: <20210720150716.1213775-1-robdclark@gmail.com> <60ffb6f3-e932-d9af-3b90-81adf0c15250@gmail.com> In-Reply-To: From: Daniel Vetter Date: Wed, 21 Jul 2021 09:59:20 +0200 Message-ID: Subject: Re: [Linaro-mm-sig] [PATCH] drm/msm: Add fence->wait() op To: Rob Clark Cc: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel , Rob Clark , "open list:DRM DRIVER FOR MSM ADRENO GPU" , David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , =?UTF-8?Q?Christian_K=C3=B6nig?= , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Sean Paul , "open list:DMA BUFFER SHARING FRAMEWORK" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 21, 2021 at 12:32 AM Rob Clark wrote: > > On Tue, Jul 20, 2021 at 1:55 PM Daniel Vetter wrote: > > > > On Tue, Jul 20, 2021 at 8:26 PM Rob Clark wrote: > > > > > > On Tue, Jul 20, 2021 at 11:03 AM Christian K=C3=B6nig > > > wrote: > > > > > > > > Hi Rob, > > > > > > > > Am 20.07.21 um 17:07 schrieb Rob Clark: > > > > > From: Rob Clark > > > > > > > > > > Somehow we had neither ->wait() nor dma_fence_signal() calls, and= no > > > > > one noticed. Oops. > > > > > > > > > > > > I'm not sure if that is a good idea. > > > > > > > > The dma_fence->wait() callback is pretty much deprecated and should= not > > > > be used any more. > > > > > > > > What exactly do you need that for? > > > > > > Well, the alternative is to track the set of fences which have > > > signalling enabled, and then figure out which ones to signal, which > > > seems like a lot more work, vs just re-purposing the wait > > > implementation we already have for non-dma_fence cases ;-) > > > > > > Why is the ->wait() callback (pretty much) deprecated? > > > > Because if you need it that means for your driver dma_fence_add_cb is > > broken, which means a _lot_ of things don't work. Like dma_buf poll > > (compositors have patches to start using that), and I think > > drm/scheduler also becomes rather unhappy. > > I'm starting to page back in how this works.. fence cb's aren't broken > (which is also why dma_fence_wait() was not completely broken), > because in retire_submits() we call > dma_fence_is_signaled(submit->hw_fence). > > But the reason that the custom wait function cleans up a tiny bit of > jank is that the wait_queue_head_t gets signaled earlier, before we > start iterating the submits and doing all that retire_submit() stuff > (unpin/unref bo's, etc). I suppose I could just split things up to > call dma_fence_signal() earlier, and *then* do the retire_submits() > stuff. Yeah reducing the latency there sounds like a good idea. -Daniel > > BR, > -R > > > It essentially exists only for old drivers where ->enable_signalling > > is unreliable and we paper over that with a retry loop in ->wait and > > pray no one notices that it's too butchered. The proper fix is to have > > a driver thread to guarantee that ->enable_signalling works reliable, > > so you don't need a ->wait. > > > > Can you type up a kerneldoc patch for dma_fence_ops->wait to hammer > > this in please? > > -Daniel > > > > > > > > BR, > > > -R > > > > > > > Regards, > > > > Christian. > > > > > > > > > > > > > > Note that this removes the !timeout case, which has not been used= in > > > > > a long time. > > > > > > > > > > > > > > > > > > Signed-off-by: Rob Clark > > > > > --- > > > > > drivers/gpu/drm/msm/msm_fence.c | 59 +++++++++++++++++++-------= ------- > > > > > 1 file changed, 34 insertions(+), 25 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/ms= m/msm_fence.c > > > > > index cd59a5918038..8ee96b90ded6 100644 > > > > > --- a/drivers/gpu/drm/msm/msm_fence.c > > > > > +++ b/drivers/gpu/drm/msm/msm_fence.c > > > > > @@ -38,11 +38,10 @@ static inline bool fence_completed(struct msm= _fence_context *fctx, uint32_t fenc > > > > > return (int32_t)(fctx->completed_fence - fence) >=3D 0; > > > > > } > > > > > > > > > > -/* legacy path for WAIT_FENCE ioctl: */ > > > > > -int msm_wait_fence(struct msm_fence_context *fctx, uint32_t fenc= e, > > > > > - ktime_t *timeout, bool interruptible) > > > > > +static signed long wait_fence(struct msm_fence_context *fctx, ui= nt32_t fence, > > > > > + signed long remaining_jiffies, bool interruptible) > > > > > { > > > > > - int ret; > > > > > + signed long ret; > > > > > > > > > > if (fence > fctx->last_fence) { > > > > > DRM_ERROR_RATELIMITED("%s: waiting on invalid fence= : %u (of %u)\n", > > > > > @@ -50,33 +49,34 @@ int msm_wait_fence(struct msm_fence_context *= fctx, uint32_t fence, > > > > > return -EINVAL; > > > > > } > > > > > > > > > > - if (!timeout) { > > > > > - /* no-wait: */ > > > > > - ret =3D fence_completed(fctx, fence) ? 0 : -EBUSY; > > > > > + if (interruptible) { > > > > > + ret =3D wait_event_interruptible_timeout(fctx->even= t, > > > > > + fence_completed(fctx, fence), > > > > > + remaining_jiffies); > > > > > } else { > > > > > - unsigned long remaining_jiffies =3D timeout_to_jiff= ies(timeout); > > > > > - > > > > > - if (interruptible) > > > > > - ret =3D wait_event_interruptible_timeout(fc= tx->event, > > > > > - fence_completed(fctx, fence), > > > > > - remaining_jiffies); > > > > > - else > > > > > - ret =3D wait_event_timeout(fctx->event, > > > > > - fence_completed(fctx, fence), > > > > > - remaining_jiffies); > > > > > - > > > > > - if (ret =3D=3D 0) { > > > > > - DBG("timeout waiting for fence: %u (complet= ed: %u)", > > > > > - fence, fctx->completed_fenc= e); > > > > > - ret =3D -ETIMEDOUT; > > > > > - } else if (ret !=3D -ERESTARTSYS) { > > > > > - ret =3D 0; > > > > > - } > > > > > + ret =3D wait_event_timeout(fctx->event, > > > > > + fence_completed(fctx, fence), > > > > > + remaining_jiffies); > > > > > + } > > > > > + > > > > > + if (ret =3D=3D 0) { > > > > > + DBG("timeout waiting for fence: %u (completed: %u)"= , > > > > > + fence, fctx->completed_fence); > > > > > + ret =3D -ETIMEDOUT; > > > > > + } else if (ret !=3D -ERESTARTSYS) { > > > > > + ret =3D 0; > > > > > } > > > > > > > > > > return ret; > > > > > } > > > > > > > > > > +/* legacy path for WAIT_FENCE ioctl: */ > > > > > +int msm_wait_fence(struct msm_fence_context *fctx, uint32_t fenc= e, > > > > > + ktime_t *timeout, bool interruptible) > > > > > +{ > > > > > + return wait_fence(fctx, fence, timeout_to_jiffies(timeout),= interruptible); > > > > > +} > > > > > + > > > > > /* called from workqueue */ > > > > > void msm_update_fence(struct msm_fence_context *fctx, uint32_t = fence) > > > > > { > > > > > @@ -114,10 +114,19 @@ static bool msm_fence_signaled(struct dma_f= ence *fence) > > > > > return fence_completed(f->fctx, f->base.seqno); > > > > > } > > > > > > > > > > +static signed long msm_fence_wait(struct dma_fence *fence, bool = intr, > > > > > + signed long timeout) > > > > > +{ > > > > > + struct msm_fence *f =3D to_msm_fence(fence); > > > > > + > > > > > + return wait_fence(f->fctx, fence->seqno, timeout, intr); > > > > > +} > > > > > + > > > > > static const struct dma_fence_ops msm_fence_ops =3D { > > > > > .get_driver_name =3D msm_fence_get_driver_name, > > > > > .get_timeline_name =3D msm_fence_get_timeline_name, > > > > > .signaled =3D msm_fence_signaled, > > > > > + .wait =3D msm_fence_wait, > > > > > }; > > > > > > > > > > struct dma_fence * > > > > > > > > > > > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > http://blog.ffwll.ch --=20 Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch