Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp17215pxv; Wed, 21 Jul 2021 14:12:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx2BlMrK2aftMS4YACES+iBzZqv7esctI1ERJST6FwEQrHjuk98oMJcCgH0sdMpU+dKpVIS X-Received: by 2002:a02:b60a:: with SMTP id h10mr33171822jam.6.1626901537040; Wed, 21 Jul 2021 14:05:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626901537; cv=none; d=google.com; s=arc-20160816; b=SRhHByPQgzA04Xe+fvSS1aQQJDeUm9rfbrGCqyzYEo0SdtrgmNS6kyNalKsOM7zVEF ov2FUOW/duDynq9aIL8/tRo4Wqe9FxXuzisZeoi9cIY+laxhYoP1Ba/PcBtWmtua+m5M P8z2jGAluOaWQQsbQS+sEwGpSTwaC5RQc/one9jaAjIil964Obebn/8+M9Q14sbenzA1 B7pOkd159S1Y31tMehM4+gU2IxSG+caGr+pyLk14MWkffLa7TEtbjP6PX0MIPe9100vR UUijVxAFchcZnn8iVHcXMxAZMgcrUt8BZDRrfCeekRxmLygqgJv3d4Dw5Qs9v+F7vrmZ ZTSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from; bh=62lIbW7ALTJU9m/yr5HwUIV/SiM+TbAwKY2PXPyFo5k=; b=qEj69PQa003xY/Prj6qHJGOzattxS+eFP4K0NeYeTSRD/4ob7aS4J5QXKH/JU8LtsT iXOW97D9iqnY0V991odVW3frwMndQaIH6R+nMdAylJrPJ4afhcGlhFb+7X6Xc2ViNFBy 4G0PQ4nRH+RDPgUUqEue8B2XRy0ptKdie4qELzRWIluHeB3xIx9wI7iaGhOGnJCGAlo3 0BzCUIyvdu/MfqrKOl3CkbC1eYbChE1NtQrn9vIQ+KmvtYKhNk+KgK1rFFnYGJ31aB2A kF+Yr3QNEFJHKtIY0Ae11BRr4LiIb/FAaFb/4F1BDSeT1ShlUKXT//dcAz274UrZfCzg nOVw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w25si28223957jaq.39.2021.07.21.14.05.25; Wed, 21 Jul 2021 14:05:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238795AbhGUSfe (ORCPT + 99 others); Wed, 21 Jul 2021 14:35:34 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:11112 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231633AbhGUSfe (ORCPT ); Wed, 21 Jul 2021 14:35:34 -0400 X-IronPort-AV: E=Sophos;i="5.84,258,1620658800"; d="scan'208";a="88348859" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 22 Jul 2021 04:16:09 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 17339400854C; Thu, 22 Jul 2021 04:16:06 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Rob Herring , Linus Walleij , Magnus Damm , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 0/4] pin and gpio controller driver for Renesas RZ/G2L Date: Wed, 21 Jul 2021 20:15:54 +0100 Message-Id: <20210721191558.22484-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi All, This patch series adds pin and gpio controller driver for Renesas RZ/G2L SoC. RZ/G2L has a simple pin and GPIO controller combined similar to RZ/A2. This patch series applies on top of Linux 5.14-rc2 Cheers, Prabhakar Changes for v3: * Dropped clock patch from the series (its queued up already in renesas-clk-for-v5.15) * Included ACK form Geert for binding patch * Fixed review comments pointed by Geert * Fixed s/property/properties for patch 4/4 pointed by Sergei Changes for v2: * Added support for per pin pinmux support * Added support for pins to set configs * Dropped pfc-r9a07g044.c/h * Fixed review comments pointed by Geert * Included clock/reset changes * Included DTS/I changes Lad Prabhakar (4): dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Add DT bindings for RZ/G2L pinctrl pinctrl: renesas: Add RZ/G2L pin and gpio controller driver arm64: dts: renesas: r9a07g044: Add pinctrl node arm64: dts: renesas: rzg2l-smarc: Add scif0 pins .../pinctrl/renesas,rzg2l-pinctrl.yaml | 155 +++ arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 13 + arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 10 + drivers/pinctrl/renesas/Kconfig | 11 + drivers/pinctrl/renesas/Makefile | 1 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 1163 +++++++++++++++++ include/dt-bindings/pinctrl/rzg2l-pinctrl.h | 23 + 7 files changed, 1376 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml create mode 100644 drivers/pinctrl/renesas/pinctrl-rzg2l.c create mode 100644 include/dt-bindings/pinctrl/rzg2l-pinctrl.h base-commit: 2734d6c1b1a089fb593ef6a23d4b70903526fe0c -- 2.17.1