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[23.128.96.18]) by mx.google.com with ESMTP id eb21si19703261ejc.626.2021.07.22.14.11.33; Thu, 22 Jul 2021 14:11:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=fail header.i=@quicinc.com header.s=qcdkim header.b="fSkrF/fO"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231585AbhGVU3k (ORCPT + 99 others); Thu, 22 Jul 2021 16:29:40 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:63516 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231154AbhGVU3f (ORCPT ); Thu, 22 Jul 2021 16:29:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1626988210; x=1658524210; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=zzVHvsy9guulRS91R6eWfP1dC1lWmabuPtdlztmGJNs=; b=fSkrF/fOb4SbXPzbQXApnCoNyGeWV2gVGCFHaDBKWII6nOqJJqxiOQv0 JjxwbU0v1xj8jdxWZIhiaE8FPvebj7m+LUBQwHUGMHqaRg53M4Ns02e+S kWnCps2PYbfw04ix0MrziMZQY8M5ch1aYF8ITsT36qBRSfY89vC5cu2I8 A=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 22 Jul 2021 14:10:09 -0700 X-QCInternal: smtphost Received: from nasanexm03e.na.qualcomm.com ([10.85.0.48]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 22 Jul 2021 14:10:09 -0700 Received: from vamslank1-linux.qualcomm.com (10.80.80.8) by nasanexm03e.na.qualcomm.com (10.85.0.48) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Thu, 22 Jul 2021 14:10:08 -0700 From: To: , , , , , , CC: , , , , "Vamsi Krishna Lanka" Subject: [PATCH v2 0/6] Add Pdc, GCC and RPMh clock support for SDX65 Date: Thu, 22 Jul 2021 14:09:37 -0700 Message-ID: X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanexm03e.na.qualcomm.com (10.85.0.48) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Vamsi Krishna Lanka Hello, Changes from v1: - Addressed Bjorn's comments related to the GCC support patch - Collected Bjorn's and Rob's Reviewed-by for the dt-bindings patches This patch series adds bindings and device driver changes for GCC, pdc and RPMh clock support for SDX65 Platform. Thanks, Vamsi Vamsi Krishna Lanka (2): clk: qcom: Add new PLL type for SDX65 clk: qcom: Add SDX65 GCC support Vamsi krishna Lanka (4): dt-bindings: clock: Add SDX65 GCC clock bindings dt-bindings: clock: Introduce RPMHCC bindings for SDX65 clk: qcom: Add support for SDX65 RPMh clocks dt-bindings: clock: Introduce pdc bindings for SDX65 .../bindings/clock/qcom,gcc-sdx65.yaml | 79 + .../bindings/clock/qcom,rpmhcc.yaml | 1 + .../interrupt-controller/qcom,pdc.txt | 1 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 170 ++ drivers/clk/qcom/clk-alpha-pll.h | 4 + drivers/clk/qcom/clk-rpmh.c | 27 + drivers/clk/qcom/gcc-sdx65.c | 1597 +++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdx65.h | 122 ++ 10 files changed, 2010 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml create mode 100644 drivers/clk/qcom/gcc-sdx65.c create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx65.h -- 2.32.0