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[23.128.96.18]) by mx.google.com with ESMTP id y13si26036724ilu.34.2021.07.23.02.43.26; Fri, 23 Jul 2021 02:43:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231365AbhGWJBx (ORCPT + 99 others); Fri, 23 Jul 2021 05:01:53 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:46008 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231231AbhGWJBs (ORCPT ); Fri, 23 Jul 2021 05:01:48 -0400 X-UUID: eebc860940f74451840a8c455f649121-20210723 X-UUID: eebc860940f74451840a8c455f649121-20210723 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 517431591; Fri, 23 Jul 2021 17:42:14 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 23 Jul 2021 17:42:12 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 23 Jul 2021 17:42:11 +0800 From: Christine Zhu To: , , , CC: , , , , , , , , Christine Zhu Subject: [v6,2/3] dt-bindings: reset: mt8195: add toprgu reset-controller header file Date: Fri, 23 Jul 2021 17:41:37 +0800 Message-ID: <20210723094138.24793-3-Christine.Zhu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210723094138.24793-1-Christine.Zhu@mediatek.com> References: <20210723094138.24793-1-Christine.Zhu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add toprgu reset-controller header file for MT8195 platform Signed-off-by: Christine Zhu --- .../reset-controller/mt8195-resets.h | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8195-resets.h diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset-controller/mt8195-resets.h new file mode 100644 index 000000000000..8176a3e5063f --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8195-resets.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either licens + * + * Copyright (c) 2021 MediaTek Inc. + * Author: Christine Zhu + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 + +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 +#define MT8195_TOPRGU_APU_SW_RST 2 +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 +#define MT8195_TOPRGU_MMSYS_SW_RST 7 +#define MT8195_TOPRGU_MFG_SW_RST 8 +#define MT8195_TOPRGU_VENC_SW_RST 9 +#define MT8195_TOPRGU_VDEC_SW_RST 10 +#define MT8195_TOPRGU_IMG_SW_RST 11 +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 +#define MT8195_TOPRGU_AUDIO_SW_RST 14 +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 +#define MT8195_TOPRGU_EDPTX_SW_RST 16 +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 +#define MT8195_TOPRGU_DPTX_SW_RST 22 +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 + +#define MT8195_TOPRGU_SW_RST_NUM 16 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ -- 2.18.0