Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp1652240pxv; Fri, 23 Jul 2021 13:55:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxbFgjlJDk7k2EFIQwTs7wqYh7MS9CIiBQ1UpFqAZur6MmavCRAyAjNSahgYaMQIIAhw9RQ X-Received: by 2002:a05:6402:4c5:: with SMTP id n5mr7686933edw.322.1627073704411; Fri, 23 Jul 2021 13:55:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627073704; cv=none; d=google.com; s=arc-20160816; b=OhSVd+ovQVv3HVMRxXUYsveRvbRPqbhraV5+pqpVOidWoJuWczi1K6GvzETSBTWjc/ /MwOjGA0sA0bE18b1wxDYL3bnZ32mwKrTdrQ6r4DwGX+pxNsRhvMJJCwmXq4nvTKfEY+ bD0KD+hP2AJnP7nQSXDJrwt236xKLyQNvbPID+hrDSgrC3A1gQ0eqs3ShiHcPny/bWdo J97TYwkbM+/MTuazZvNiQpTgxfvcJRitBFcph0pzEc4pNJhhOawZhtZc/LK8KTbCX008 j9gU6PpFk0w9rFMS5nlXg2+azepDBibhhKDaExb2b4Uo7OecOmaxnqaNNNz+GloNWy4t GBgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=muC2gzs6t16nyfv2lQpd+rqeS97ljqfrQp9QNKO53pM=; b=J1Ig4EF7bcQKw8XVk0HgHkAbzPbT3fhNOLZg2UiFNd590OK8QqSXD9ZHlL8/Wd7wIU 2uEkEoLfm8H2K0jsK3FAlUDJCVsJXaDUTv+Ek6INmdICy/FweCZhqFjSEZv4l+v7QDLj ASQqTUjeRAdVvHogZMmbhjsJje20s96su4czhz95cryEEm5Z9Hc5tu/sPg1HYiIs8gcs qqCJJm5CB3iWdLvr1uSNCulud5HE2cbdBxqAHsz+m4Jc0euYVbKg6nRZ6FKGz4OIlc98 O8P0m4QlPfKRsWuRChaRvX28amh13EYUGjoEZC/bZvM/fUR9wwpL2Kbmz2PVuyBJVn/R nhJw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t19si8731036eji.162.2021.07.23.13.54.41; Fri, 23 Jul 2021 13:55:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231948AbhGWUJq (ORCPT + 99 others); Fri, 23 Jul 2021 16:09:46 -0400 Received: from finn.gateworks.com ([108.161.129.64]:57758 "EHLO finn.localdomain" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231488AbhGWUJi (ORCPT ); Fri, 23 Jul 2021 16:09:38 -0400 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1m727R-0057Vc-KE; Fri, 23 Jul 2021 20:50:05 +0000 From: Tim Harvey To: Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Lorenzo Pieralisi Cc: Tim Harvey Subject: [PATCH 4/6] reset: imx7: add resets for PCIe Date: Fri, 23 Jul 2021 13:49:56 -0700 Message-Id: <20210723204958.7186-5-tharvey@gateworks.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210723204958.7186-1-tharvey@gateworks.com> References: <20210723204958.7186-1-tharvey@gateworks.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add reset for PCIe clock and PHY. Signed-off-by: Tim Harvey --- drivers/reset/reset-imx7.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index 185a333df66c..423707e1fd59 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -191,6 +191,7 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) }, [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, + [IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ] = { SRC_PCIEPHY_RCR, BIT(4) }, [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, @@ -234,7 +235,9 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev, udelay(10); break; + case IMX8MQ_RESET_PCIEPHY_PERST: case IMX8MQ_RESET_PCIE_CTRL_APPS_EN: + case IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ: case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: -- 2.17.1