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Fri, 23 Jul 2021 21:12:01 -0700 (PDT) Received: from thinkpad ([2409:4072:6d0b:3004:b3d2:21bb:b6c1:27fa]) by smtp.gmail.com with ESMTPSA id b1sm7319151pjn.11.2021.07.23.21.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jul 2021 21:11:59 -0700 (PDT) Date: Sat, 24 Jul 2021 09:41:50 +0530 From: Manivannan Sadhasivam To: Mauro Carvalho Chehab Cc: Vinod Koul , Bjorn Helgaas , Rob Herring , linuxarm@huawei.com, mauro.chehab@huawei.com, Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Binghui Wang , Lorenzo Pieralisi , Rob Herring , Wei Xu , Xiaowei Song , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v7 08/10] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Message-ID: <20210724041150.GA4053@thinkpad> References: <20210722133628.GC4446@workstation> <20210723085318.243f155f@coco.lan> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210723085318.243f155f@coco.lan> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 23, 2021 at 08:53:18AM +0200, Mauro Carvalho Chehab wrote: > Em Thu, 22 Jul 2021 19:06:28 +0530 > Manivannan Sadhasivam escreveu: > > > On Wed, Jul 21, 2021 at 10:39:10AM +0200, Mauro Carvalho Chehab wrote: > > > From: Manivannan Sadhasivam > > > > > > Add DTS bindings for the HiKey 970 board's PCIe hardware. > > > > > > Co-developed-by: Mauro Carvalho Chehab > > > Signed-off-by: Manivannan Sadhasivam > > > Signed-off-by: Mauro Carvalho Chehab > > > --- > > > arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++ > > > .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - > > > drivers/pci/controller/dwc/pcie-kirin.c | 12 ---- > > > 3 files changed, 71 insertions(+), 13 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi > > > index 1f228612192c..6dfcfcfeedae 100644 > > > --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi > > > +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi > > > @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { > > > #clock-cells = <1>; > > > }; > > > > > > + pmctrl: pmctrl@fff31000 { > > > + compatible = "hisilicon,hi3670-pmctrl", "syscon"; > > > + reg = <0x0 0xfff31000 0x0 0x1000>; > > > + #clock-cells = <1>; > > > + }; > > > + > > > > Irrelevant change to this patch. > > Huh? > > This is used by PCIe PHY, as part of the power on procedures: > > +static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable) > +{ > + struct device *dev = phy->dev; > + u32 time = 100; > + unsigned int val = NOC_PW_MASK; > + int rst; > + > + if (enable) > + val = NOC_PW_MASK | NOC_PW_SET_BIT; > + else > + val = NOC_PW_MASK; > + rst = enable ? 1 : 0; > + > + regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val); > > Ah... you're hardcoding the syscon compatible in driver. Sorry missed that. But if these syscon nodes are independent memory regions or belong to non PCI/PHY memory map, you could've fetched the reference through a DT property along with the offset then used it in driver. Like, pcie_phy: pcie-phy@fc000000 { ... hisilicon,noc-power-regs = <&pmctrl 0x38c>; hisilicon,sctrl-cmos-regs = <&sctrl 0x60>; ... }; The benefit of doing this way is, if the pmctrl, sctrl register layout changes in future, you can handle it without any issues. > > > > > > iomcu: iomcu@ffd7e000 { > > > compatible = "hisilicon,hi3670-iomcu", "syscon"; > > > reg = <0x0 0xffd7e000 0x0 0x1000>; > > > @@ -660,6 +666,71 @@ gpio28: gpio@fff1d000 { > > > clock-names = "apb_pclk"; > > > }; > > > > > > > [...] > > > > > + #interrupt-cells = <1>; > > > + interrupts = <0 283 4>; > > > > Use the DT flag for interrupts instead of hardcoded value > > Do you mean like this? > > interrupts = <0 283 IRQ_TYPE_LEVEL_HIGH>; > yes but you could also use, interrupts = ; Thanks, Mani