Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp2691459pxv; Sun, 25 Jul 2021 02:21:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyhnodW5fuYCo2xG056K0jb4orRMrU4KL0jket5J4FUEQQC0nEU1UtBlORAGXw5VJiH143r X-Received: by 2002:a92:6805:: with SMTP id d5mr8834624ilc.286.1627204909516; Sun, 25 Jul 2021 02:21:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627204909; cv=none; d=google.com; s=arc-20160816; b=NeYMSSo3sjz2xwqLJAK/n5s4IfzrxginzjdKcdKnbl6X8vWJNMytGda9A10tyBU/VV fXdnKBfrxLjYpu/qzMrWSNajb989ghDulMX5AhzGD/AIio9w2aurH0O0ygicLGbTIYHd 7t8AuiHtAPs0prM/fSdN0ivJOGY8E/g79OKI4re4rAN6vxAVjTbkUs5UW44VHSkI5FNN xq5tuZ/JX+amqYzIQNa3K6z8BpGT/n23PzyL4N+qveQlko9GrxOqYC33YzOESFlyXEWd SWo9jMH4zptsv6BdgyIXbWGh/NgWfhXVFV6fT8z+xTd92CBnmvp7Q6st6DLcyTxqjTqB Nm5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:content-transfer-encoding:mime-version :subject:from:references:in-reply-to:message-id:date:dkim-signature; bh=a2jLfTu5I0pf7yG+N2kAepV5pO0M4U1zK0ilSpaBN6o=; b=qsBdv6w6WkuQgvvueVGyzs155j9T3+c2pidyZzz6owtl33GmQAfVUeBcyuzrp/N1Mq Xuy/hAUgr8tbMZsMkFoSfjauwEyUEdfn2y0axCpGAchjjqsivMESS62KkKlJG1pFHBKD LO8PQ0AMHhgZ/63IW7ThiBFSgg3EoigmNnQ/X2m1NDH89b9XXBKIbDkFrijEWAMT4hOn saqPbJNibgk404Wq5OVilS1csn8jo+P6U2yn373NkV9X/6XE9DeQhgPw10MXn2SzY5IV kF/35xwsi+egDpuQol78axtqfSR/NGHQwawt/vNQfCCjHrut8oHbTZW/pO51iT1B7TM+ rtZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rere.qmqm.pl header.s=1 header.b=nuL5GcHr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=rere.qmqm.pl Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q18si7131307jao.21.2021.07.25.02.21.38; Sun, 25 Jul 2021 02:21:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@rere.qmqm.pl header.s=1 header.b=nuL5GcHr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=rere.qmqm.pl Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230433AbhGYIkX (ORCPT + 99 others); Sun, 25 Jul 2021 04:40:23 -0400 Received: from rere.qmqm.pl ([91.227.64.183]:7280 "EHLO rere.qmqm.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230305AbhGYIkS (ORCPT ); Sun, 25 Jul 2021 04:40:18 -0400 Received: from remote.user (localhost [127.0.0.1]) by rere.qmqm.pl (Postfix) with ESMTPSA id 4GXcwv5CbVz8d; Sun, 25 Jul 2021 11:20:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=rere.qmqm.pl; s=1; t=1627204847; bh=d04TklBqxwEHnvQPkhgUpAZEHT2VwJgiULJvHpgtAWA=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=nuL5GcHrE4Y1ZQ+bLGhNiKHD4KWkpBlBXofzNdrf8yUNRV9pz9wOS9h6yh2g4/o8e KVYljTQ6I9+gSJO8AyQaT0U8xbg+UJ5uPVsVqEaBohcb2S9x4KhG7hApIDhNm5oH90 JxWD+mGvmk1tZjWjnffl0SKMf/Yn1vxDKj3GiEb73vZP3kC0FegxBh8NnyO9OySlcH ISfvZKiCJ8LORWxfAAqAlAWA+qcmORXvBi+obJca21oHo6ocaUdp0Nm46pVyJp44mG K0dPPImsX7NfYKjWDCeC+u5uEIxspfjoW/eZUHqgjcHuxfCuLGJepOjOMYBw4bzFBz ezCNfHWF8Bh5g== X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.2 at mail Date: Sun, 25 Jul 2021 11:20:47 +0200 Message-Id: In-Reply-To: References: From: =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Subject: [PATCH v4 1/5] mmc: sdhci: fix base clock usage in preset value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To: Ulf Hansson , Kevin Liu , Michal Simek , Suneel Garapati Cc: Adrian Hunter , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Al Cooper Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fixed commit added an unnecessary read of CLOCK_CONTROL. The value read is overwritten for programmable clock preset, but is carried over for divided clock preset. This can confuse sdhci_enable_clk() if the register has enable bits set for some reason at time time of clock calculation. Remove the read. Quoting Al Cooper: sdhci_brcmstb_set_clock() assumed that sdhci_calc_clk() would always return the divider value without the enable set, so this fixes a case for DDR52 where the enable was not being cleared when the divider value was changed. Cc: stable@vger.kernel.org Fixes: 52983382c74f ("mmc: sdhci: enhance preset value function") Signed-off-by: Michał Mirosław Acked-by: Al Cooper --- v4: no changes v3: updated commit message v2: removed truncated sentence from commitmsg Signed-off-by: Michał Mirosław --- drivers/mmc/host/sdhci.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index aba6e10b8605..c7438dd13e3e 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1857,7 +1857,6 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, if (host->preset_enabled) { u16 pre_val; - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); pre_val = sdhci_get_preset_value(host); div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val); if (host->clk_mul && -- 2.30.2