Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
From:   Zev Weiss <zweiss@equinix.com>
To:     Iwona Winiarska <iwona.winiarska@intel.com>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>,
        "linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
        "linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
        Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>,
        Mauro Carvalho Chehab <mchehab@kernel.org>,
        Jonathan Corbet <corbet@lwn.net>,
        "x86@kernel.org" <x86@kernel.org>,
        Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>,
        Ingo Molnar <mingo@redhat.com>,
        Guenter Roeck <linux@roeck-us.net>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        Jean Delvare <jdelvare@suse.com>,
        Rob Herring <robh+dt@kernel.org>,
        Borislav Petkov <bp@alien8.de>,
        Andy Lutomirski <luto@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-hwmon@vger.kernel.org" <linux-hwmon@vger.kernel.org>,
        Tony Luck <tony.luck@intel.com>,
        Andrew Jeffery <andrew@aj.id.au>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Yazen Ghannam <yazen.ghannam@amd.com>
Subject: Re: [PATCH 11/14] hwmon: peci: Add cputemp driver
Thread-Topic: [PATCH 11/14] hwmon: peci: Add cputemp driver
Thread-Index: AQHXgrX5rzpUzdTFsE2/Bu/x34QZOw==
Date:   Tue, 27 Jul 2021 07:06:52 +0000
Message-ID: <20210727070651.GP8018@packtop>
References: <20210712220447.957418-1-iwona.winiarska@intel.com>
 <20210712220447.957418-12-iwona.winiarska@intel.com>
In-Reply-To: <20210712220447.957418-12-iwona.winiarska@intel.com>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-antispam-messagedata-chunkcount: 1
x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?OWWmOaJi3fbm8yjUoHbP/jhldml/qDw+Ot8EukcxfRYWetmexUHjEq5XBYIv?=
 =?us-ascii?Q?MFD/qJgTQWx6uQVAmKrTN5V3DhyDYhRFnBWdr5Y3LJAIJ/2NL+tPGoiDOCtu?=
 =?us-ascii?Q?dlACXZFYWg3kigFE/rt5OlXzAU1QtCZL2AGLp0HIqZLLtwIbRWdEXwIbJ+Tj?=
 =?us-ascii?Q?3her+a0zOJrMllsK72IMmeoyB/A/iZZP9o4xAZGcJhT1YhTYNifBeO79AKc4?=
 =?us-ascii?Q?K1Yw+6nnwRwFEm6zoMoF1LRDyVxiEI/aE6i6ouknWHVSbtN/SaPztNfIRLoY?=
 =?us-ascii?Q?vgu7zRoD3VgKCgqQ41mUbm9Ym2u90mPI0dswB59o5u4/RDUcDnBEVywF/6+I?=
 =?us-ascii?Q?/47GJFKDdObJKTfjmWjAG5ef9dCfeS92+D2E8r8NWoCVr5VeiAK2LTZapfV5?=
 =?us-ascii?Q?8DJMn5On8TrUyF0geNl8LP0LCGSn/gXASPvxQYIis/iJTF72E0MdeCpL4t9N?=
 =?us-ascii?Q?d641ovnYKGs+1ErC5j3ZYzLhxAYE4KtxZc2UMehymYycCBunRwQHC/LF780p?=
 =?us-ascii?Q?l7aC4f9wRvrQvTfhPE0EvuMQnaHvye4LzBG4y+9b3fQq+XCBo52HUDGFXSL0?=
 =?us-ascii?Q?K+H23YVgzpahPLZbg2LdfVCOJlndxWYuiLgdXWa8lQwdeh7k3OBTBI0Szr1U?=
 =?us-ascii?Q?s4MJg7i/HgVnL12pAbJ6FfUr1hThxal2UFF0yBuigPGrPGL+Iclz5oSbzGAo?=
 =?us-ascii?Q?TC7RtivcegFYusifte8Ex/x2vrbB+BqDTKr2BpPdioFic+z4z2ITZJqlbmn7?=
 =?us-ascii?Q?TJ6kft8ICENnq/tjEgFM2NgN8aVZk16iIji+52gTxktYBysvZTbmHr/ckPub?=
 =?us-ascii?Q?ZbmsURAw4tgcfawhjVGL8N17qe9LNNkZ8DMjgweiD+jQ1uRRS4n/pFlg9SKX?=
 =?us-ascii?Q?wdLeNNfBhSA26mf65r4LIfhXUOgVTF1bcN4+aNjjT72IP+ZdZXgUkcZVWik3?=
 =?us-ascii?Q?AIhuGhGGpKxXNRsa0b4jxR5bhcvbJUO4VGDcWXkrcYWyn08mkvqKWV7dVYai?=
 =?us-ascii?Q?Gfj9zVkZoIZQRSveOX4P8t8XnbPvFFawjqrWk29mVGskP/JSc7jqyRzp+FFq?=
 =?us-ascii?Q?T2L7UhxSPMrJLesyPODT4ICEhv8QRimer/GkoHim4xcawrbUKecRz6paIDWJ?=
 =?us-ascii?Q?BjWydmsHMpxO5FLvKpVn3r+vOnflw7TEDfdG04y9ryCpC0Y6hfi9wJz8Rznx?=
 =?us-ascii?Q?Vz4HUoPCOMTfGd8YDi0FCOb/PKSYqwfGfeKE6DqayFPcmPI9Pf5PRApZB4Xr?=
 =?us-ascii?Q?bscmQlWkIOkMyw9Wt156FQt2L6IsB0HZvsTd9WB2qgSmO5dmgU3SjN6o0gqS?=
 =?us-ascii?Q?UFYH4evgsVib9t0rJdfURagR?=
x-ms-exchange-transport-forked: True
Content-Type: text/plain; charset="us-ascii"
Content-ID: <8E9F04616B01BE47A3F0FD586ABB4F53@namprd04.prod.outlook.com>
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: equinix.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: DM8PR04MB8007.namprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 768376fd-8800-459c-053c-08d950cd1c8f
X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Jul 2021 07:06:52.5172
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 72adb271-2fc7-4afe-a5ee-9de6a59f6bfb
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: nZuu2jqbYhlW4fIWBLtgKVJ1SFtjUJpqBusPEhsyjWO6ft7fh1Sw55vYXzOVD5N8+wf41Tixjkc0nECtfmLF9Q==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR04MB7797
X-Proofpoint-ORIG-GUID: UOE7OGRKfVwWBdTd8FxbX8G2peGexglu
X-Proofpoint-GUID: UOE7OGRKfVwWBdTd8FxbX8G2peGexglu
X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.790
 definitions=2021-07-27_05:2021-07-27,2021-07-27 signatures=0
X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0
 impostorscore=0 mlxscore=0 clxscore=1015 phishscore=0 priorityscore=1501
 spamscore=0 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 adultscore=0
 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1
 engine=8.12.0-2107140000 definitions=main-2107270039
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, Jul 12, 2021 at 05:04:44PM CDT, Iwona Winiarska wrote:
>Add peci-cputemp driver for Digital Thermal Sensor (DTS) thermal
>readings of the processor package and processor cores that are
>accessible via the PECI interface.
>
>The main use case for the driver (and PECI interface) is out-of-band
>management, where we're able to obtain the DTS readings from an external
>entity connected with PECI, e.g. BMC on server platforms.
>
>Co-developed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
>Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
>Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
>Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
>---
> MAINTAINERS                  |   7 +
> drivers/hwmon/Kconfig        |   2 +
> drivers/hwmon/Makefile       |   1 +
> drivers/hwmon/peci/Kconfig   |  18 ++
> drivers/hwmon/peci/Makefile  |   5 +
> drivers/hwmon/peci/common.h  |  46 ++++
> drivers/hwmon/peci/cputemp.c | 503 +++++++++++++++++++++++++++++++++++
> 7 files changed, 582 insertions(+)
> create mode 100644 drivers/hwmon/peci/Kconfig
> create mode 100644 drivers/hwmon/peci/Makefile
> create mode 100644 drivers/hwmon/peci/common.h
> create mode 100644 drivers/hwmon/peci/cputemp.c
>
>diff --git a/MAINTAINERS b/MAINTAINERS
>index f47b5f634293..35ba9e3646bd 100644
>--- a/MAINTAINERS
>+++ b/MAINTAINERS
>@@ -14504,6 +14504,13 @@ L:	platform-driver-x86@vger.kernel.org
> S:	Maintained
> F:	drivers/platform/x86/peaq-wmi.c
>
>+PECI HARDWARE MONITORING DRIVERS
>+M:	Iwona Winiarska <iwona.winiarska@intel.com>
>+R:	Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
>+L:	linux-hwmon@vger.kernel.org
>+S:	Supported
>+F:	drivers/hwmon/peci/
>+
> PECI SUBSYSTEM
> M:	Iwona Winiarska <iwona.winiarska@intel.com>
> R:	Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
>diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
>index e3675377bc5d..61c0e3404415 100644
>--- a/drivers/hwmon/Kconfig
>+++ b/drivers/hwmon/Kconfig
>@@ -1507,6 +1507,8 @@ config SENSORS_PCF8591
> 	  These devices are hard to detect and rarely found on mainstream
> 	  hardware. If unsure, say N.
>
>+source "drivers/hwmon/peci/Kconfig"
>+
> source "drivers/hwmon/pmbus/Kconfig"
>
> config SENSORS_PWM_FAN
>diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
>index d712c61c1f5e..f52331f212ed 100644
>--- a/drivers/hwmon/Makefile
>+++ b/drivers/hwmon/Makefile
>@@ -202,6 +202,7 @@ obj-$(CONFIG_SENSORS_WM8350)	+=3D wm8350-hwmon.o
> obj-$(CONFIG_SENSORS_XGENE)	+=3D xgene-hwmon.o
>
> obj-$(CONFIG_SENSORS_OCC)	+=3D occ/
>+obj-$(CONFIG_SENSORS_PECI)	+=3D peci/
> obj-$(CONFIG_PMBUS)		+=3D pmbus/
>
> ccflags-$(CONFIG_HWMON_DEBUG_CHIP) :=3D -DDEBUG
>diff --git a/drivers/hwmon/peci/Kconfig b/drivers/hwmon/peci/Kconfig
>new file mode 100644
>index 000000000000..e10eed68d70a
>--- /dev/null
>+++ b/drivers/hwmon/peci/Kconfig
>@@ -0,0 +1,18 @@
>+# SPDX-License-Identifier: GPL-2.0-only
>+
>+config SENSORS_PECI_CPUTEMP
>+	tristate "PECI CPU temperature monitoring client"
>+	depends on PECI
>+	select SENSORS_PECI
>+	select PECI_CPU
>+	help
>+	  If you say yes here you get support for the generic Intel PECI
>+	  cputemp driver which provides Digital Thermal Sensor (DTS) thermal
>+	  readings of the CPU package and CPU cores that are accessible via
>+	  the processor PECI interface.
>+
>+	  This driver can also be built as a module. If so, the module
>+	  will be called peci-cputemp.
>+
>+config SENSORS_PECI
>+	tristate
>diff --git a/drivers/hwmon/peci/Makefile b/drivers/hwmon/peci/Makefile
>new file mode 100644
>index 000000000000..e8a0ada5ab1f
>--- /dev/null
>+++ b/drivers/hwmon/peci/Makefile
>@@ -0,0 +1,5 @@
>+# SPDX-License-Identifier: GPL-2.0-only
>+
>+peci-cputemp-y :=3D cputemp.o
>+
>+obj-$(CONFIG_SENSORS_PECI_CPUTEMP)	+=3D peci-cputemp.o
>diff --git a/drivers/hwmon/peci/common.h b/drivers/hwmon/peci/common.h
>new file mode 100644
>index 000000000000..54580c100d06
>--- /dev/null
>+++ b/drivers/hwmon/peci/common.h
>@@ -0,0 +1,46 @@
>+/* SPDX-License-Identifier: GPL-2.0-only */
>+/* Copyright (c) 2021 Intel Corporation */
>+
>+#include <linux/types.h>
>+
>+#ifndef __PECI_HWMON_COMMON_H
>+#define __PECI_HWMON_COMMON_H
>+
>+#define UPDATE_INTERVAL_DEFAULT		HZ
>+
>+/**
>+ * struct peci_sensor_data - PECI sensor information
>+ * @valid: flag to indicate the sensor value is valid
>+ * @value: sensor value in milli units
>+ * @last_updated: time of the last update in jiffies
>+ */
>+struct peci_sensor_data {
>+	unsigned int valid;

From what I can see it looks like the 'valid' member here is strictly a
one-shot has-this-value-ever-been-set indicator, which seems a bit
wasteful to keep around forever post initialization; couldn't the same
information be inferred from checking last_updated !=3D 0 or something?

>+	s32 value;
>+	unsigned long last_updated;
>+};
>+
>+/**
>+ * peci_sensor_need_update() - check whether sensor update is needed or n=
ot
>+ * @sensor: pointer to sensor data struct
>+ *
>+ * Return: true if update is needed, false if not.
>+ */
>+
>+static inline bool peci_sensor_need_update(struct peci_sensor_data *senso=
r)
>+{
>+	return !sensor->valid ||
>+	       time_after(jiffies, sensor->last_updated + UPDATE_INTERVAL_DEFAUL=
T);
>+}
>+
>+/**
>+ * peci_sensor_mark_updated() - mark the sensor is updated
>+ * @sensor: pointer to sensor data struct
>+ */
>+static inline void peci_sensor_mark_updated(struct peci_sensor_data *sens=
or)
>+{
>+	sensor->valid =3D 1;
>+	sensor->last_updated =3D jiffies;
>+}
>+
>+#endif /* __PECI_HWMON_COMMON_H */
>diff --git a/drivers/hwmon/peci/cputemp.c b/drivers/hwmon/peci/cputemp.c
>new file mode 100644
>index 000000000000..56a526471687
>--- /dev/null
>+++ b/drivers/hwmon/peci/cputemp.c
>@@ -0,0 +1,503 @@
>+// SPDX-License-Identifier: GPL-2.0-only
>+// Copyright (c) 2018-2021 Intel Corporation
>+
>+#include <linux/auxiliary_bus.h>
>+#include <linux/bitfield.h>
>+#include <linux/bitops.h>
>+#include <linux/hwmon.h>
>+#include <linux/jiffies.h>
>+#include <linux/module.h>
>+#include <linux/peci.h>
>+#include <linux/peci-cpu.h>
>+#include <linux/units.h>
>+#include <linux/x86/intel-family.h>
>+
>+#include "common.h"
>+
>+#define CORE_NUMS_MAX		64
>+
>+#define DEFAULT_CHANNEL_NUMS	5

DEFAULT_ seems like a slightly odd prefix for this (it's not something
that can really be overridden or anything); would BASE_ perhaps be a bit
more appropriate?

>+#define CORETEMP_CHANNEL_NUMS	CORE_NUMS_MAX
>+#define CPUTEMP_CHANNEL_NUMS	(DEFAULT_CHANNEL_NUMS + CORETEMP_CHANNEL_NUM=
S)
>+
>+#define TEMP_TARGET_FAN_TEMP_MASK	GENMASK(15, 8)
>+#define TEMP_TARGET_REF_TEMP_MASK	GENMASK(23, 16)
>+#define TEMP_TARGET_TJ_OFFSET_MASK	GENMASK(29, 24)
>+
>+#define DTS_MARGIN_MASK		GENMASK(15, 0)
>+#define PCS_MODULE_TEMP_MASK	GENMASK(15, 0)
>+
>+#define DTS_FIXED_POINT_FRACTION	64
>+
>+struct resolved_cores_reg {
>+	u8 bus;
>+	u8 dev;
>+	u8 func;
>+	u8 offset;
>+};
>+
>+struct cpu_info {
>+	struct resolved_cores_reg *reg;
>+	u8 min_peci_revision;

As with the dimmtemp driver, min_peci_revision appears unused here,
though in this case if it were removed there'd only be one (pointer)
member left in struct cpu_info, so we could perhaps remove it as well
and then also a level of indirection in peci_cputemp_ids/cpu_{hsx,icx}
too?

>+};
>+
>+struct peci_cputemp {
>+	struct peci_device *peci_dev;
>+	struct device *dev;
>+	const char *name;
>+	const struct cpu_info *gen_info;
>+	struct {
>+		struct peci_sensor_data die;
>+		struct peci_sensor_data dts;
>+		struct peci_sensor_data tcontrol;
>+		struct peci_sensor_data tthrottle;
>+		struct peci_sensor_data tjmax;
>+		struct peci_sensor_data core[CORETEMP_CHANNEL_NUMS];
>+	} temp;
>+	const char **coretemp_label;
>+	DECLARE_BITMAP(core_mask, CORE_NUMS_MAX);
>+};
>+
>+enum cputemp_channels {
>+	channel_die,
>+	channel_dts,
>+	channel_tcontrol,
>+	channel_tthrottle,
>+	channel_tjmax,
>+	channel_core,
>+};
>+
>+static const char *cputemp_label[DEFAULT_CHANNEL_NUMS] =3D {

static const char * const cputemp_label?  (That is, const pointer to
const char, rather than non-const pointer to const char.)

>+	"Die",
>+	"DTS",
>+	"Tcontrol",
>+	"Tthrottle",
>+	"Tjmax",
>+};
>+
>+static int get_temp_targets(struct peci_cputemp *priv)
>+{
>+	s32 tthrottle_offset, tcontrol_margin;
>+	u32 pcs;
>+	int ret;
>+
>+	/*
>+	 * Just use only the tcontrol marker to determine if target values need
>+	 * update.
>+	 */
>+	if (!peci_sensor_need_update(&priv->temp.tcontrol))
>+		return 0;
>+
>+	ret =3D peci_pcs_read(priv->peci_dev, PECI_PCS_TEMP_TARGET, 0, &pcs);
>+	if (ret)
>+		return ret;
>+
>+	priv->temp.tjmax.value =3D FIELD_GET(TEMP_TARGET_REF_TEMP_MASK, pcs) * M=
ILLIDEGREE_PER_DEGREE;
>+
>+	tcontrol_margin =3D FIELD_GET(TEMP_TARGET_FAN_TEMP_MASK, pcs);
>+	tcontrol_margin =3D sign_extend32(tcontrol_margin, 7) * MILLIDEGREE_PER_=
DEGREE;
>+	priv->temp.tcontrol.value =3D priv->temp.tjmax.value - tcontrol_margin;
>+
>+	tthrottle_offset =3D FIELD_GET(TEMP_TARGET_TJ_OFFSET_MASK, pcs) * MILLID=
EGREE_PER_DEGREE;
>+	priv->temp.tthrottle.value =3D priv->temp.tjmax.value - tthrottle_offset=
;
>+
>+	peci_sensor_mark_updated(&priv->temp.tcontrol);
>+
>+	return 0;
>+}
>+
>+/*
>+ * Processors return a value of DTS reading in S10.6 fixed point format
>+ * (sign, 10 bits signed integer value, 6 bits fractional).

This parenthetical reads to me like it's describing 17 bits -- I'm not a
PECI expert, but from my reading of the (somewhat skimpy) docs I've got
on it I'd suggest a description more like "sign, 9-bit magnitude, 6-bit
fraction".

>+ * Error codes:
>+ *   0x8000: General sensor error
>+ *   0x8001: Reserved
>+ *   0x8002: Underflow on reading value
>+ *   0x8003-0x81ff: Reserved
>+ */
>+static bool dts_valid(s32 val)
>+{
>+	return val < 0x8000 || val > 0x81ff;
>+}
>+
>+static s32 dts_to_millidegree(s32 val)
>+{
>+	return sign_extend32(val, 15) * MILLIDEGREE_PER_DEGREE / DTS_FIXED_POINT=
_FRACTION;
>+}
>+
>+static int get_die_temp(struct peci_cputemp *priv)
>+{
>+	s16 temp;
>+	int ret;
>+
>+	if (!peci_sensor_need_update(&priv->temp.die))
>+		return 0;
>+
>+	ret =3D peci_temp_read(priv->peci_dev, &temp);
>+	if (ret)
>+		return ret;
>+
>+	if (!dts_valid(temp))
>+		return -EIO;
>+
>+	/* Note that the tjmax should be available before calling it */
>+	priv->temp.die.value =3D priv->temp.tjmax.value + dts_to_millidegree(tem=
p);
>+
>+	peci_sensor_mark_updated(&priv->temp.die);
>+
>+	return 0;
>+}
>+
>+static int get_dts(struct peci_cputemp *priv)
>+{
>+	s32 dts_margin;
>+	u32 pcs;
>+	int ret;
>+
>+	if (!peci_sensor_need_update(&priv->temp.dts))
>+		return 0;
>+
>+	ret =3D peci_pcs_read(priv->peci_dev, PECI_PCS_THERMAL_MARGIN, 0, &pcs);
>+	if (ret)
>+		return ret;
>+
>+	dts_margin =3D FIELD_GET(DTS_MARGIN_MASK, pcs);
>+	if (!dts_valid(dts_margin))
>+		return -EIO;
>+
>+	/* Note that the tcontrol should be available before calling it */
>+	priv->temp.dts.value =3D priv->temp.tcontrol.value - dts_to_millidegree(=
dts_margin);
>+
>+	peci_sensor_mark_updated(&priv->temp.dts);
>+
>+	return 0;
>+}
>+
>+static int get_core_temp(struct peci_cputemp *priv, int core_index)
>+{
>+	s32 core_dts_margin;
>+	u32 pcs;
>+	int ret;
>+
>+	if (!peci_sensor_need_update(&priv->temp.core[core_index]))
>+		return 0;
>+
>+	ret =3D peci_pcs_read(priv->peci_dev, PECI_PCS_MODULE_TEMP, core_index, =
&pcs);
>+	if (ret)
>+		return ret;
>+
>+	core_dts_margin =3D FIELD_GET(PCS_MODULE_TEMP_MASK, pcs);
>+	if (!dts_valid(core_dts_margin))
>+		return -EIO;
>+
>+	/* Note that the tjmax should be available before calling it */
>+	priv->temp.core[core_index].value =3D
>+		priv->temp.tjmax.value + dts_to_millidegree(core_dts_margin);
>+
>+	peci_sensor_mark_updated(&priv->temp.core[core_index]);
>+
>+	return 0;
>+}
>+
>+static int cputemp_read_string(struct device *dev, enum hwmon_sensor_type=
s type,
>+			       u32 attr, int channel, const char **str)
>+{
>+	struct peci_cputemp *priv =3D dev_get_drvdata(dev);
>+
>+	if (attr !=3D hwmon_temp_label)
>+		return -EOPNOTSUPP;
>+
>+	*str =3D channel < channel_core ?
>+		cputemp_label[channel] : priv->coretemp_label[channel - channel_core];
>+
>+	return 0;
>+}
>+
>+static int cputemp_read(struct device *dev, enum hwmon_sensor_types type,
>+			u32 attr, int channel, long *val)
>+{
>+	struct peci_cputemp *priv =3D dev_get_drvdata(dev);
>+	int ret, core_index;
>+
>+	ret =3D get_temp_targets(priv);
>+	if (ret)
>+		return ret;
>+
>+	switch (attr) {
>+	case hwmon_temp_input:
>+		switch (channel) {
>+		case channel_die:
>+			ret =3D get_die_temp(priv);
>+			if (ret)
>+				return ret;
>+
>+			*val =3D priv->temp.die.value;
>+			break;
>+		case channel_dts:
>+			ret =3D get_dts(priv);
>+			if (ret)
>+				return ret;
>+
>+			*val =3D priv->temp.dts.value;
>+			break;
>+		case channel_tcontrol:
>+			*val =3D priv->temp.tcontrol.value;
>+			break;
>+		case channel_tthrottle:
>+			*val =3D priv->temp.tthrottle.value;
>+			break;
>+		case channel_tjmax:
>+			*val =3D priv->temp.tjmax.value;
>+			break;
>+		default:
>+			core_index =3D channel - channel_core;
>+			ret =3D get_core_temp(priv, core_index);
>+			if (ret)
>+				return ret;
>+
>+			*val =3D priv->temp.core[core_index].value;
>+			break;
>+		}
>+		break;
>+	case hwmon_temp_max:
>+		*val =3D priv->temp.tcontrol.value;
>+		break;
>+	case hwmon_temp_crit:
>+		*val =3D priv->temp.tjmax.value;
>+		break;
>+	case hwmon_temp_crit_hyst:
>+		*val =3D priv->temp.tjmax.value - priv->temp.tcontrol.value;
>+		break;
>+	default:
>+		return -EOPNOTSUPP;
>+	}
>+
>+	return 0;
>+}
>+
>+static umode_t cputemp_is_visible(const void *data, enum hwmon_sensor_typ=
es type,
>+				  u32 attr, int channel)
>+{
>+	const struct peci_cputemp *priv =3D data;
>+
>+	if (channel > CPUTEMP_CHANNEL_NUMS)
>+		return 0;
>+
>+	if (channel < channel_core)
>+		return 0444;
>+
>+	if (test_bit(channel - channel_core, priv->core_mask))
>+		return 0444;
>+
>+	return 0;
>+}
>+
>+static int init_core_mask(struct peci_cputemp *priv)
>+{
>+	struct peci_device *peci_dev =3D priv->peci_dev;
>+	struct resolved_cores_reg *reg =3D priv->gen_info->reg;
>+	u64 core_mask;
>+	u32 data;
>+	int ret;
>+
>+	/* Get the RESOLVED_CORES register value */
>+	switch (peci_dev->info.model) {
>+	case INTEL_FAM6_ICELAKE_X:
>+	case INTEL_FAM6_ICELAKE_D:
>+		ret =3D peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev,
>+					     reg->func, reg->offset + 4, &data);
>+		if (ret)
>+			return ret;
>+
>+		core_mask =3D (u64)data << 32;
>+
>+		ret =3D peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev,
>+					     reg->func, reg->offset, &data);
>+		if (ret)
>+			return ret;
>+
>+		core_mask |=3D data;
>+
>+		break;
>+	default:
>+		ret =3D peci_pci_local_read(peci_dev, reg->bus, reg->dev,
>+					  reg->func, reg->offset, &data);
>+		if (ret)
>+			return ret;
>+
>+		core_mask =3D data;
>+
>+		break;
>+	}
>+
>+	if (!core_mask)
>+		return -EIO;
>+
>+	bitmap_from_u64(priv->core_mask, core_mask);
>+
>+	return 0;
>+}
>+
>+static int create_temp_label(struct peci_cputemp *priv)
>+{
>+	unsigned long core_max =3D find_last_bit(priv->core_mask, CORE_NUMS_MAX)=
;
>+	int i;
>+
>+	priv->coretemp_label =3D devm_kzalloc(priv->dev, core_max * sizeof(char =
*), GFP_KERNEL);
>+	if (!priv->coretemp_label)
>+		return -ENOMEM;
>+
>+	for_each_set_bit(i, priv->core_mask, CORE_NUMS_MAX) {
>+		priv->coretemp_label[i] =3D devm_kasprintf(priv->dev, GFP_KERNEL, "Core=
 %d", i);
>+		if (!priv->coretemp_label[i])
>+			return -ENOMEM;
>+	}
>+
>+	return 0;
>+}
>+
>+static void check_resolved_cores(struct peci_cputemp *priv)
>+{
>+	int ret;
>+
>+	ret =3D init_core_mask(priv);
>+	if (ret)
>+		return;
>+
>+	ret =3D create_temp_label(priv);
>+	if (ret)
>+		bitmap_zero(priv->core_mask, CORE_NUMS_MAX);
>+}
>+
>+static const struct hwmon_ops peci_cputemp_ops =3D {
>+	.is_visible =3D cputemp_is_visible,
>+	.read_string =3D cputemp_read_string,
>+	.read =3D cputemp_read,
>+};
>+
>+static const u32 peci_cputemp_temp_channel_config[] =3D {
>+	/* Die temperature */
>+	HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_CRI=
T_HYST,
>+	/* DTS margin */
>+	HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_CRI=
T_HYST,
>+	/* Tcontrol temperature */
>+	HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_CRIT,
>+	/* Tthrottle temperature */
>+	HWMON_T_LABEL | HWMON_T_INPUT,
>+	/* Tjmax temperature */
>+	HWMON_T_LABEL | HWMON_T_INPUT,
>+	/* Core temperature - for all core channels */
>+	[channel_core ... CPUTEMP_CHANNEL_NUMS - 1] =3D HWMON_T_LABEL | HWMON_T_=
INPUT,
>+	0
>+};
>+
>+static const struct hwmon_channel_info peci_cputemp_temp_channel =3D {
>+	.type =3D hwmon_temp,
>+	.config =3D peci_cputemp_temp_channel_config,
>+};
>+
>+static const struct hwmon_channel_info *peci_cputemp_info[] =3D {
>+	&peci_cputemp_temp_channel,
>+	NULL
>+};
>+
>+static const struct hwmon_chip_info peci_cputemp_chip_info =3D {
>+	.ops =3D &peci_cputemp_ops,
>+	.info =3D peci_cputemp_info,
>+};
>+
>+static int peci_cputemp_probe(struct auxiliary_device *adev,
>+			      const struct auxiliary_device_id *id)
>+{
>+	struct device *dev =3D &adev->dev;
>+	struct peci_device *peci_dev =3D to_peci_device(dev->parent);
>+	struct peci_cputemp *priv;
>+	struct device *hwmon_dev;
>+
>+	priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>+	if (!priv)
>+		return -ENOMEM;
>+
>+	priv->name =3D devm_kasprintf(dev, GFP_KERNEL, "peci_cputemp.cpu%d",
>+				    peci_dev->info.socket_id);
>+	if (!priv->name)
>+		return -ENOMEM;
>+
>+	dev_set_drvdata(dev, priv);
>+	priv->dev =3D dev;
>+	priv->peci_dev =3D peci_dev;
>+	priv->gen_info =3D (const struct cpu_info *)id->driver_data;
>+
>+	check_resolved_cores(priv);
>+
>+	hwmon_dev =3D devm_hwmon_device_register_with_info(priv->dev, priv->name=
,
>+							 priv, &peci_cputemp_chip_info, NULL);
>+
>+	return PTR_ERR_OR_ZERO(hwmon_dev);
>+}
>+
>+static struct resolved_cores_reg resolved_cores_reg_hsx =3D {
>+	.bus =3D 1,
>+	.dev =3D 30,
>+	.func =3D 3,
>+	.offset =3D 0xb4,
>+};
>+
>+static struct resolved_cores_reg resolved_cores_reg_icx =3D {
>+	.bus =3D 14,
>+	.dev =3D 30,
>+	.func =3D 3,
>+	.offset =3D 0xd0,
>+};
>+
>+static const struct cpu_info cpu_hsx =3D {
>+	.reg		=3D &resolved_cores_reg_hsx,
>+	.min_peci_revision =3D 0x30,
>+};
>+
>+static const struct cpu_info cpu_icx =3D {
>+	.reg		=3D &resolved_cores_reg_icx,
>+	.min_peci_revision =3D 0x40,
>+};
>+
>+static const struct auxiliary_device_id peci_cputemp_ids[] =3D {
>+	{
>+		.name =3D "peci_cpu.cputemp.hsx",
>+		.driver_data =3D (kernel_ulong_t)&cpu_hsx,
>+	},
>+	{
>+		.name =3D "peci_cpu.cputemp.bdx",
>+		.driver_data =3D (kernel_ulong_t)&cpu_hsx,
>+	},
>+	{
>+		.name =3D "peci_cpu.cputemp.bdxd",
>+		.driver_data =3D (kernel_ulong_t)&cpu_hsx,
>+	},
>+	{
>+		.name =3D "peci_cpu.cputemp.skx",
>+		.driver_data =3D (kernel_ulong_t)&cpu_hsx,
>+	},
>+	{
>+		.name =3D "peci_cpu.cputemp.icx",
>+		.driver_data =3D (kernel_ulong_t)&cpu_icx,
>+	},
>+	{
>+		.name =3D "peci_cpu.cputemp.icxd",
>+		.driver_data =3D (kernel_ulong_t)&cpu_icx,
>+	},
>+	{ }
>+};
>+MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids);
>+
>+static struct auxiliary_driver peci_cputemp_driver =3D {
>+	.probe		=3D peci_cputemp_probe,
>+	.id_table	=3D peci_cputemp_ids,
>+};
>+
>+module_auxiliary_driver(peci_cputemp_driver);
>+
>+MODULE_AUTHOR("Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>");
>+MODULE_AUTHOR("Iwona Winiarska <iwona.winiarska@intel.com>");
>+MODULE_DESCRIPTION("PECI cputemp driver");
>+MODULE_LICENSE("GPL");
>+MODULE_IMPORT_NS(PECI_CPU);
>--=20
>2.31.1
>=