Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp4312435pxv; Tue, 27 Jul 2021 04:26:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyI+7uh2J3vY6bw+/QZUWs0JPmSDGczY86S6NStmmJNKSywBJoTIPgWNBnAoR6IjVEuR1ic X-Received: by 2002:a05:6e02:d09:: with SMTP id g9mr11470012ilj.153.1627385169001; Tue, 27 Jul 2021 04:26:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627385168; cv=none; d=google.com; s=arc-20160816; b=ulryj8/0quBBak5VN80Y7kgc6XXclHxhtsGeWtyb8W0v19ku62uuGjDeMPDH3/Ihrl xxvLaUsn8nvTr16U0HzZoX+g7qQs7R3YVPSn8furl3I9pe8jNddLKvpaNU9ZbpOCQOqm e/ORZZ9KSChHdnGSSp/NpNsTHEYC7tc1AUY7z4keYWfTy+2imdkY/MXgNM87p9TXvNwb DoYo55n0ak+Mkv6PJUVo69SwDoKee4Cv+F646xyYc3Xs2XMvkDeCGC4pZ0fNVcB1ib0v 9y8PpnIvAds3lwJR6XsvnA+i24JF37K7oXbb8yY9a2fdss5TEezQS8uSgOMwnWHLSe8X fVYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=G5AzMp6mVRwUmPTeQkOrvTNiTpoVgg2+LTf1q8pEH1M=; b=jRgqxe3NhHyxVjLBYaMKD4CAqNR3HnPM3xJHdTLxA9865XIp4/OSkMGAohYevn9i0s y3KC7gN4XmoQhsSYeP/6zCS3+wuTxitfmgq6KhF8v7tpEx4h2WTetGQhJ32PU87YjS/n Eey95AIJpgUv8UF2GAmASpRRzDynj864wqzmKgapkaSv2ZyZuTbuTDjjZ5zs1H1bJnty eBa/FJrnX1ksVsm3tP3oQAfXcxNve3WmznapwhlYyLx9zEDINDCsS0Jh5mVlSu8+Axyw bq2wFKfkPIzTjfQ6TAAy5wGX8zEd1BKl2OxOxsnXFailddPaB+GRX5urZS0GLbnXgYsI Pv2Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z4si3024961ilo.41.2021.07.27.04.25.57; Tue, 27 Jul 2021 04:26:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236541AbhG0LX4 (ORCPT + 99 others); Tue, 27 Jul 2021 07:23:56 -0400 Received: from relmlor1.renesas.com ([210.160.252.171]:33438 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236514AbhG0LXw (ORCPT ); Tue, 27 Jul 2021 07:23:52 -0400 X-IronPort-AV: E=Sophos;i="5.84,273,1620658800"; d="scan'208";a="88912066" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 27 Jul 2021 20:23:51 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 6595C400C433; Tue, 27 Jul 2021 20:23:49 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Rob Herring , Linus Walleij , Magnus Damm , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v4 3/4] arm64: dts: renesas: r9a07g044: Add pinctrl node Date: Tue, 27 Jul 2021 12:23:27 +0100 Message-Id: <20210727112328.18809-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210727112328.18809-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20210727112328.18809-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add GPIO/pinctrl node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 01482d227506..17afb4bb6261 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -111,6 +111,19 @@ status = "disabled"; }; + pinctrl: pin-controller@11030000 { + compatible = "renesas,r9a07g044-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 392>; + clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_GPIO_RSTN>, + <&cpg R9A07G044_GPIO_PORT_RESETN>, + <&cpg R9A07G044_GPIO_SPARE_RESETN>; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- 2.17.1