Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp4704479pxv; Tue, 27 Jul 2021 14:16:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx6Q0xFTXFwjD2890qp0KKx5+ql5f9ZMTVt+rm2ORZvvKt3bern9X+aNVjgT5J5cG429BfI X-Received: by 2002:a17:907:3e03:: with SMTP id hp3mr22042959ejc.183.1627420603293; Tue, 27 Jul 2021 14:16:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627420603; cv=none; d=google.com; s=arc-20160816; b=fMbw8+izie4HEbqaEN4uVZaeQJErSD1v6/YKyQBUtYxay7HVAwUyjWVUqP4jYJp+ZE KZ9uxgFqGG6Yhir/CpOpj9Z16Qi/OWaEu7LRC+uf4SpdeHIWGJeodSaHY+ONNAar+NNY KRwQqJhuQ63HI3a9ipqzjdl9DKFW2mKDTR75RPwVae6iZN+IGJorQu0VEnuTxZSZWtRZ nqUQDXQUG7YeeaSAF4qAXpMizHUfX0hyCmQgAz3Sf4Fqw3g54ixrlj5MgZrCoh1ZROGR bfnRLZ8fwD6Y+6Pn6GUGH1Gl7Mdepf/e7/jnz9ly5EG/rVkK7waGhYrj2urX4+LSKsAg s7VQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6mvxUJ87sudxyMnXk+SNmSJl9hv8ghFMGniXKOiMPtw=; b=h3TPKLDCTHzbNqOS5+ofTzFkRwdsBjU9G9Fhd7TQcpUfcIZyYZ54SiFDTJkVGnpuyy yBzIXj3Aq35K95wDgHt2j/4f+9HvyDolxM+zvQ+WB3ja0h89dSRbhbZENHN2tKQ7WDRd vIKsurkvDSGh1z/glekP3PsYy4cNfcqvZ/l41L2voAa6GsAu4xAYrDIbJtV1h2tyn0of rddAmnaQ2I99m0lAdddpbyLZLrU1qK4o66BNf9MDaKNbt0T6zixEnrXSDsltfqpbu2HX p5cxR0BNqud+LKz4dGN7f6stdv4/XA82XZWkf8t8JTYCg4RqhMoV1l3dBnoo2NA6Yevb OmLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=tG9Wekqb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u25si4115436edq.517.2021.07.27.14.16.20; Tue, 27 Jul 2021 14:16:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=tG9Wekqb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232214AbhG0VNX (ORCPT + 99 others); Tue, 27 Jul 2021 17:13:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231339AbhG0VNW (ORCPT ); Tue, 27 Jul 2021 17:13:22 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FDB4C061757; Tue, 27 Jul 2021 14:13:21 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id t21so17570243plr.13; Tue, 27 Jul 2021 14:13:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6mvxUJ87sudxyMnXk+SNmSJl9hv8ghFMGniXKOiMPtw=; b=tG9WekqbBueWHLkIaofNI4gJul/Ff/LZEIIRon+7eeHH7dxCEXnE8PCmGkTPgTCzVo XtQvndCanVJ0+n1YwrTx2ZRjAXOFT6z0wzixrW5wRmIUVAyndD7jC7gv0zyafFFoB3f6 BtcEZi5j8k2gPE6CGhMf7uHVd6x9baVvFrUpPUTNQkqIioU8QDm4bo4tRogTUtUxw2iQ ZvIgK8fHCbW0kyBozaOHpnklgpB85APCVzst8/8oxtV01jhc7V0EXaXh20jj6B+9cRYp OR4uI+ZdkJvEm9o2vAoD9K3UKsdCr5PmDzBrIfrlw/OFD+civsEkBq6PL3te8JUfpOX+ WgDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6mvxUJ87sudxyMnXk+SNmSJl9hv8ghFMGniXKOiMPtw=; b=Hw5STqu5A3wlM74bwugx/PrqSbsd9r9w0xQP+IsnirNTqP38q8LMvzcBJOIfbuLOnq fvtKLpvpOZ8V7kIMciA6/TYP/v1IASV+6l0JgTyE1eWYUeN4JCDcEUO+HbcywMBkpB8J 5o8EPdNL9VJjUp2K4QK6lpyzkh4j50pkjTDeEGxv3YOL3SppvZy6XcCTvkg6p3yFBapq /V/ccTlCQSYVsnhvv6yDTYL4D6bpQrZtrqBdaPP0d9LG1jACjtdv9v47VqoMeo1VHlyH oR+ycMK/bJuS1dctzw+9nuG9DtcPJ/la7lLWrTGdbgo2ZW5eUSSLXTQbxQ0M1T2RiAQW uDBQ== X-Gm-Message-State: AOAM5330LTz842xiZkSpCgJA78P/DZzJGPmAqS4PMNzuNyzfQa8VbjfI AAuKDW8FmrRVOJCTqueIcXUgDfvnXYZzNw== X-Received: by 2002:a17:90a:e558:: with SMTP id ei24mr10926413pjb.97.1627420400775; Tue, 27 Jul 2021 14:13:20 -0700 (PDT) Received: from localhost (c-73-25-156-94.hsd1.or.comcast.net. [73.25.156.94]) by smtp.gmail.com with ESMTPSA id 143sm4922203pfz.13.2021.07.27.14.13.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jul 2021 14:13:19 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: Daniel Vetter , Matthew Brost , =?UTF-8?q?Michel=20D=C3=A4nzer?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , Rob Clark , Rob Clark , Sean Paul , David Airlie , Sumit Semwal , =?UTF-8?q?Christian=20K=C3=B6nig?= , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), freedreno@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list), linux-media@vger.kernel.org (open list:DMA BUFFER SHARING FRAMEWORK), linaro-mm-sig@lists.linaro.org (moderated list:DMA BUFFER SHARING FRAMEWORK) Subject: [RFC 5/4] drm/msm: Add deadline based boost support Date: Tue, 27 Jul 2021 14:17:33 -0700 Message-Id: <20210727211733.2601469-1-robdclark@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210726233854.2453899-1-robdclark@gmail.com> References: <20210726233854.2453899-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rob Clark Signed-off-by: Rob Clark --- This is a quick implementation of what I had in mind for driver side of deadline boost. For a couple games with bad gpu devfreq behavior this boosts "Render quality" from ~35% to ~95%. (The "Render quality" metric in chrome://arc-overview-tracing is basically a measure of the deviation in frame/commit time, so 100% would be a consistent fps with no variantion.) Not quite 100%, this is still a bit of a re- active mechanism. A similar result can be had by tuning devfreq to boost to max OPP at a much lower threshold of busyness. With the obvious downside that you spend a lot of time running the GPU much faster than needed. drivers/gpu/drm/msm/msm_fence.c | 76 +++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_fence.h | 20 +++++++ drivers/gpu/drm/msm/msm_gpu.h | 1 + drivers/gpu/drm/msm/msm_gpu_devfreq.c | 20 +++++++ 4 files changed, 117 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c index f2cece542c3f..67c2a96e1c85 100644 --- a/drivers/gpu/drm/msm/msm_fence.c +++ b/drivers/gpu/drm/msm/msm_fence.c @@ -8,6 +8,37 @@ #include "msm_drv.h" #include "msm_fence.h" +#include "msm_gpu.h" + +static inline bool fence_completed(struct msm_fence_context *fctx, uint32_t fence); + +static struct msm_gpu *fctx2gpu(struct msm_fence_context *fctx) +{ + struct msm_drm_private *priv = fctx->dev->dev_private; + return priv->gpu; +} + +static enum hrtimer_restart deadline_timer(struct hrtimer *t) +{ + struct msm_fence_context *fctx = container_of(t, + struct msm_fence_context, deadline_timer); + + kthread_queue_work(fctx2gpu(fctx)->worker, &fctx->deadline_work); + + return HRTIMER_NORESTART; +} + +static void deadline_work(struct kthread_work *work) +{ + struct msm_fence_context *fctx = container_of(work, + struct msm_fence_context, deadline_work); + + /* If deadline fence has already passed, nothing to do: */ + if (fence_completed(fctx, fctx->next_deadline_fence)) + return; + + msm_devfreq_boost(fctx2gpu(fctx), 2); +} struct msm_fence_context * @@ -26,6 +57,13 @@ msm_fence_context_alloc(struct drm_device *dev, volatile uint32_t *fenceptr, fctx->fenceptr = fenceptr; spin_lock_init(&fctx->spinlock); + hrtimer_init(&fctx->deadline_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); + fctx->deadline_timer.function = deadline_timer; + + kthread_init_work(&fctx->deadline_work, deadline_work); + + fctx->next_deadline = ktime_get(); + return fctx; } @@ -49,6 +87,8 @@ void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence) { spin_lock(&fctx->spinlock); fctx->completed_fence = max(fence, fctx->completed_fence); + if (fence_completed(fctx, fctx->next_deadline_fence)) + hrtimer_cancel(&fctx->deadline_timer); spin_unlock(&fctx->spinlock); } @@ -79,10 +119,46 @@ static bool msm_fence_signaled(struct dma_fence *fence) return fence_completed(f->fctx, f->base.seqno); } +static void msm_fence_set_deadline(struct dma_fence *fence, ktime_t deadline) +{ + struct msm_fence *f = to_msm_fence(fence); + struct msm_fence_context *fctx = f->fctx; + unsigned long flags; + ktime_t now; + + spin_lock_irqsave(&fctx->spinlock, flags); + now = ktime_get(); + + if (ktime_after(now, fctx->next_deadline) || + ktime_before(deadline, fctx->next_deadline)) { + fctx->next_deadline = deadline; + fctx->next_deadline_fence = + max(fctx->next_deadline_fence, (uint32_t)fence->seqno); + + /* + * Set timer to trigger boost 3ms before deadline, or + * if we are already less than 3ms before the deadline + * schedule boost work immediately. + */ + deadline = ktime_sub(deadline, ms_to_ktime(3)); + + if (ktime_after(now, deadline)) { + kthread_queue_work(fctx2gpu(fctx)->worker, + &fctx->deadline_work); + } else { + hrtimer_start(&fctx->deadline_timer, deadline, + HRTIMER_MODE_ABS); + } + } + + spin_unlock_irqrestore(&fctx->spinlock, flags); +} + static const struct dma_fence_ops msm_fence_ops = { .get_driver_name = msm_fence_get_driver_name, .get_timeline_name = msm_fence_get_timeline_name, .signaled = msm_fence_signaled, + .set_deadline = msm_fence_set_deadline, }; struct dma_fence * diff --git a/drivers/gpu/drm/msm/msm_fence.h b/drivers/gpu/drm/msm/msm_fence.h index 4783db528bcc..d34e853c555a 100644 --- a/drivers/gpu/drm/msm/msm_fence.h +++ b/drivers/gpu/drm/msm/msm_fence.h @@ -50,6 +50,26 @@ struct msm_fence_context { volatile uint32_t *fenceptr; spinlock_t spinlock; + + /* + * TODO this doesn't really deal with multiple deadlines, like + * if userspace got multiple frames ahead.. OTOH atomic updates + * don't queue, so maybe that is ok + */ + + /** next_deadline: Time of next deadline */ + ktime_t next_deadline; + + /** + * next_deadline_fence: + * + * Fence value for next pending deadline. The deadline timer is + * canceled when this fence is signaled. + */ + uint32_t next_deadline_fence; + + struct hrtimer deadline_timer; + struct kthread_work deadline_work; }; struct msm_fence_context * msm_fence_context_alloc(struct drm_device *dev, diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 0e4b45bff2e6..e031c9b495ed 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -425,6 +425,7 @@ void msm_devfreq_init(struct msm_gpu *gpu); void msm_devfreq_cleanup(struct msm_gpu *gpu); void msm_devfreq_resume(struct msm_gpu *gpu); void msm_devfreq_suspend(struct msm_gpu *gpu); +void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor); void msm_devfreq_active(struct msm_gpu *gpu); void msm_devfreq_idle(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c index 0a1ee20296a2..8a8d7b9028a3 100644 --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c @@ -144,6 +144,26 @@ void msm_devfreq_suspend(struct msm_gpu *gpu) devfreq_suspend_device(gpu->devfreq.devfreq); } +void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor) +{ + struct msm_gpu_devfreq *df = &gpu->devfreq; + unsigned long freq; + + /* + * Hold devfreq lock to synchronize with get_dev_status()/ + * target() callbacks + */ + mutex_lock(&df->devfreq->lock); + + freq = get_freq(gpu); + + freq *= factor; + + msm_devfreq_target(&gpu->pdev->dev, &freq, 0); + + mutex_unlock(&df->devfreq->lock); +} + void msm_devfreq_active(struct msm_gpu *gpu) { struct msm_gpu_devfreq *df = &gpu->devfreq; -- 2.31.1