Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp5025687pxv; Wed, 28 Jul 2021 01:00:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJygRDE9zu16V536AhZXgyLfFEFDIbd0mMnZP5y3Ernh8oc3skqEHJL23TykLdoQZgwoPYTU X-Received: by 2002:a05:6638:4115:: with SMTP id ay21mr25015148jab.13.1627459208974; Wed, 28 Jul 2021 01:00:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627459208; cv=none; d=google.com; s=arc-20160816; b=Fvc9B+v8Mn8Ty+zvX3UoUnz7oZ1z/lQvvTrmwoJv1ZHNRF3LnZM5jTZK0bpDfWt0gd GSmw3RxwZ1G6oNJGzlyG0LItbnXw9CYc+nv5IFloudpuSJPz9qj3UiOQhyAEZ9CdLPML Oj/5UWG8j1ydzaeRI3UXUhtVWnWU+NFN7hk1mO21s1YNpiCj0Pxxco8U6v+xCvhvVtT4 wMm04qyCyggm6xSZCUSXCqEYqqB1k5Y8HFwooIyExYVc79JDj9bwpUhhA1CJ4jSu8k8B hj3DpHxblSgi751VwWIT/O5gND5KuXUxxmisbevKhC1Ke//gyghYu+i0Cf6mFKcYFYOr /aIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=fbxnJJHE+3F4Ly2e6v+eEV+dsYVXJyKsXF5SgMtXxJM=; b=xMWlJ/ITGA4tyov/iaBny+v4auPx7ckOFcFndKBbtBg0vAFxJo1GDxJ+v8FDYYb5EZ 7gcBEdDD2UloPMfTLCEkNe96lTXUaNcFDQ1By5jaxIyupHVkwDAjjsVV6YQW9KjjacCZ vSc78ufwzf96X393ssfSVdsAXGLoq1vPNn1s6gJefbFJQeR1vE0YAf2mN19A9+lpTiDo sRMpElrU2figZwlPnO0pQp2OzRD73olj6DZPT6Xdz52IdHaFg7XGVZFW6DTxhY7DCDKS otpioF9DBMXj4e1QFddC3vhqFTxfo0KFu68MNoHqrrY5K/HJqFPZOjHPb/fHRxuxqBqF rF6A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x12si5990492iom.57.2021.07.28.00.59.58; Wed, 28 Jul 2021 01:00:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235006AbhG1H7N (ORCPT + 99 others); Wed, 28 Jul 2021 03:59:13 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:42872 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233224AbhG1H7K (ORCPT ); Wed, 28 Jul 2021 03:59:10 -0400 X-UUID: 608d5807339242e0a9f9ee9771f2dce9-20210728 X-UUID: 608d5807339242e0a9f9ee9771f2dce9-20210728 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1314977547; Wed, 28 Jul 2021 15:59:04 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 28 Jul 2021 15:59:03 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 28 Jul 2021 15:59:01 +0800 From: Chunfeng Yun To: Vinod Koul , Rob Herring , Chun-Kuang Hu CC: Chunfeng Yun , Kishon Vijay Abraham I , Philipp Zabel , Matthias Brugger , , , , , , , Eddie Hung Subject: [PATCH 1/9] dt-bindings: phy: mediatek: tphy: support type switch by pericfg Date: Wed, 28 Jul 2021 15:58:23 +0800 Message-ID: <1627459111-2907-1-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support type switch by pericfg register between USB3, PCIe, SATA, SGMII, this is used to replace the way through efuse or jumper. Signed-off-by: Chunfeng Yun --- .../devicetree/bindings/phy/mediatek,tphy.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 838852cb8527..9e6c0f43f1c6 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -201,6 +201,22 @@ patternProperties: Specify the flag to enable BC1.2 if support it type: boolean + mediatek,syscon-type: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + description: + A phandle to syscon used to access the register of type switch, + the field should always be 3 cells long. + items: + items: + - description: + The first cell represents a phandle to syscon + - description: + The second cell represents the register offset + - description: + The third cell represents the index of config segment + enum: [0, 1, 2, 3] + required: - reg - "#phy-cells" -- 2.18.0