Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp5270565pxv; Wed, 28 Jul 2021 07:07:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwS98w8q6bhmWRYSPSFwzIPPdxRSQIbBfR78iUVSwoMyH0bX1U0lAT/jiNeBLlpVUiKWfGc X-Received: by 2002:a6b:f704:: with SMTP id k4mr23976926iog.191.1627481270209; Wed, 28 Jul 2021 07:07:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627481270; cv=none; d=google.com; s=arc-20160816; b=0WDthS74aNvIFDKMiOMh8QfO7fYA3o6r6AZ848tQbcTlxIJ44Hw3caWzs4EFyrjFIq yV2qKC4vO0mc3KHdxn7t5+Hkhm8aP/iGLK8lBAr4LhgWIO83F3DUVBqHRSulgQj7EzMe pLMZCPAfdW3gYQJfE/wC0pnKOQLODEFkI0zfi7vIVrFU20yYjFeQGRAJouBKFN6mD49D OhlTvWN4KwK/UVl9cCwfnebV4BVUTRmh8jUHHjBAzt6MzGLVZ+o3Fy2L/13Aqa2/9gPS arNDn3/UtnxA7B2OuUyhWKWuIdNk8ckB5T2iefzRDcwyU2kt6abYC+CSl95NipfX8yz+ CSsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ccQQMkubByvdcW9MC94YWSCeZ0keQD8LXJ1+3XE2aiI=; b=bLdzGqllr2myUOLmdOBLT2x0huja4qEdRc9RlrhwWibv6VpY0nEKQnZUistQWP6tvf 97ygHIgEEavzcCAcJO9Qxf+sMY+Y8GSH7CmKO8/wq0ilygcMIalHsKTkIV0OpiIbNcRC B2RblVYLf7A1JdbxBE8Jk9dtoggwnyRcDwiKnJC7D2QWbyyZuB32IVjhBFJvecczB7Gc D6lXA2l0iooRi9k79cBafKpPTDLf1KgofBT6DJzOLa66y8vYao9Q5ZQWmXMnsIR8wrLX 7BSK3MF2oPGGlDv68sCeyljhzFSD2Nxiv6DfMQLKBYgPxSb8EhBZ+CAGKKNzU8L3+hZl ivEQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r3si40868jan.7.2021.07.28.07.07.38; Wed, 28 Jul 2021 07:07:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236273AbhG1OGg (ORCPT + 99 others); Wed, 28 Jul 2021 10:06:36 -0400 Received: from gloria.sntech.de ([185.11.138.130]:50104 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233439AbhG1OGg (ORCPT ); Wed, 28 Jul 2021 10:06:36 -0400 Received: from [95.90.166.74] (helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1m8kCc-0005wH-22; Wed, 28 Jul 2021 16:06:30 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Peter Geis Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Geis Subject: Re: [PATCH 6/9] arm64: dts: rockchip: add missing rk3568 cru phandles Date: Wed, 28 Jul 2021 16:06:29 +0200 Message-ID: <13247009.uLZWGnKmhe@diego> In-Reply-To: <20210728135534.703028-7-pgwipeout@gmail.com> References: <20210728135534.703028-1-pgwipeout@gmail.com> <20210728135534.703028-7-pgwipeout@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Peter, Am Mittwoch, 28. Juli 2021, 15:55:31 CEST schrieb Peter Geis: > The grf and pmugrf phandles are necessary for the pmucru and cru to > modify clocks. Add these phandles to permit adjusting the clock rates > and muxes. > > Signed-off-by: Peter Geis > --- > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index 0905fac0726a..8ba0516eedd8 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -218,6 +218,8 @@ grf: syscon@fdc60000 { > pmucru: clock-controller@fdd00000 { > compatible = "rockchip,rk3568-pmucru"; > reg = <0x0 0xfdd00000 0x0 0x1000>; > + rockchip,grf = <&grf>; > + rockchip,pmugrf = <&pmugrf>; I don't think the pmucru needs both and in fact the mainline clock driver should just reference its specific grf at all, i.e. pmucru -> pmugrf (via the rockchip,grf handle) cru -> grf I've not seen anything breaking this scope so far. Heiko > #clock-cells = <1>; > #reset-cells = <1>; > }; > @@ -225,6 +227,7 @@ pmucru: clock-controller@fdd00000 { > cru: clock-controller@fdd20000 { > compatible = "rockchip,rk3568-cru"; > reg = <0x0 0xfdd20000 0x0 0x1000>; > + rockchip,grf = <&grf>; > #clock-cells = <1>; > #reset-cells = <1>; > }; >