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From:   Peter Geis <pgwipeout@gmail.com>
Date:   Wed, 28 Jul 2021 10:18:49 -0400
Message-ID: <CAMdYzYqR+ocrXQi8TOHY0Yd2oULXuPgE_QnbcuQSw=BoaumBKA@mail.gmail.com>
Subject: Re: [PATCH 6/9] arm64: dts: rockchip: add missing rk3568 cru phandles
To:     =?UTF-8?Q?Heiko_St=C3=BCbner?= <heiko@sntech.de>
Cc:     Linus Walleij <linus.walleij@linaro.org>,
        Bartosz Golaszewski <bgolaszewski@baylibre.com>,
        Rob Herring <robh+dt@kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        devicetree@vger.kernel.org,
        arm-mail-list <linux-arm-kernel@lists.infradead.org>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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On Wed, Jul 28, 2021 at 10:06 AM Heiko St=C3=BCbner <heiko@sntech.de> wrote=
:
>
> Hi Peter,
>
> Am Mittwoch, 28. Juli 2021, 15:55:31 CEST schrieb Peter Geis:
> > The grf and pmugrf phandles are necessary for the pmucru and cru to
> > modify clocks. Add these phandles to permit adjusting the clock rates
> > and muxes.
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot=
/dts/rockchip/rk356x.dtsi
> > index 0905fac0726a..8ba0516eedd8 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > @@ -218,6 +218,8 @@ grf: syscon@fdc60000 {
> >       pmucru: clock-controller@fdd00000 {
> >               compatible =3D "rockchip,rk3568-pmucru";
> >               reg =3D <0x0 0xfdd00000 0x0 0x1000>;
> > +             rockchip,grf =3D <&grf>;
> > +             rockchip,pmugrf =3D <&pmugrf>;
>
> I don't think the pmucru needs both and in fact the mainline
> clock driver should just reference its specific grf at all, i.e.
>         pmucru -> pmugrf (via the rockchip,grf handle)
>         cru -> grf
>
> I've not seen anything breaking this scope so far.

I thought the same thing as well, but for some reason the driver
refuses to apply assigned-clocks to the plls unless these are all
present.
If the driver can get these assignments automatically eventually,
perhaps it's a loading order issue?

Thinking about it, it's probably the grf and pmugrf haven't probed
when the driver is attempting to assign these, and tying them together
forces the probe to happen first.

>
>
> Heiko
>
> >               #clock-cells =3D <1>;
> >               #reset-cells =3D <1>;
> >       };
> > @@ -225,6 +227,7 @@ pmucru: clock-controller@fdd00000 {
> >       cru: clock-controller@fdd20000 {
> >               compatible =3D "rockchip,rk3568-cru";
> >               reg =3D <0x0 0xfdd20000 0x0 0x1000>;
> > +             rockchip,grf =3D <&grf>;
> >               #clock-cells =3D <1>;
> >               #reset-cells =3D <1>;
> >       };
> >
>
>
>
>