Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp5395577pxv; Wed, 28 Jul 2021 09:43:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyIfalziZnVQFzMGVFSw/nOQIGYyiLh8wOLFCYvwHSbyWlqzlD04g9M+fZ3sncVC2GGfnkZ X-Received: by 2002:a17:907:1006:: with SMTP id ox6mr385342ejb.476.1627490614024; Wed, 28 Jul 2021 09:43:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627490614; cv=none; d=google.com; s=arc-20160816; b=mgTQFIinegqA5FZe4QflBP/lbxx4eXTbbmjoTKmktJ7F++tn0zPuVdcmQiddzS1rW1 kUrmmVtGVXdAV4cvMmVKk1J5ZbuItvDy2wh+7BGVS6McEJ2l+KouXwvhg0eXH+sRT4gl ycOyI17FnlDz8T2SeXIImJmsJDp92lEs/Fx6vO6ch4aIh5CGU4hI8SIk87AL5i5fgDaM KrXOsmJDxeJ7iZmeiAkBL41KdAmloq7MdxrpM5g33m8Ei5HI8o1kofbsVduDytAo4OWm vXIjd6KIvH8nJf9l0H4/5tzKrpS1CSbD5a+WWI/vmeCzSU+EFuIMQZ+mIJPFMDmezHQX BvnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=VbHSe5ZmokTeRZOVR5/DxbeDukJUOZWqPm1zkRBz3bc=; b=XNjQ0ex5onCHjNwqrI4kjAQxZQ4A8t4WssOKoMqprnmi3eQ4K/2wREaIHcQMKA0Yyt qqEBHSG+xicVQqhgFEpn9oUTvMTRXNCxxcib/2U2mxUtTGfCsA0vKoB7q7j8gNkPuZBy 0ibFooQi4ktFNV46PbAlxomh6TVKKtspqxw9xO2mYc4aVieOEa2OeDZZ8Iro6/fgefWR OOrtmcey/K3efT45VtO1SQwVVYHWM61pQighhjMcRFkZERMT8cWmh74clu9QGizO/36j /SP5IWGXR5S/XDSHY9JY9JakTb1ttWc3Wunc/mHp2Qi49G5Zm36kOmMnnWDM4J+yBuFA BNsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=Y0tizcCE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id nb22si285246ejc.347.2021.07.28.09.43.09; Wed, 28 Jul 2021 09:43:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=Y0tizcCE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229693AbhG1QlT (ORCPT + 99 others); Wed, 28 Jul 2021 12:41:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229574AbhG1QlT (ORCPT ); Wed, 28 Jul 2021 12:41:19 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CDB8C061757; Wed, 28 Jul 2021 09:41:17 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id m13so5077940lfg.13; Wed, 28 Jul 2021 09:41:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=VbHSe5ZmokTeRZOVR5/DxbeDukJUOZWqPm1zkRBz3bc=; b=Y0tizcCEiBh+D7lqJGorKFC0uu9mzmJ+oKCwjELrNTc3QiKdHM7vxw8UwwvMU/PaUA 53tPEf3XHrNfByM7bl/komnTjiUYQA+Ci900eyGa0vW3bBGAY1ZQna2oOVTSJ+mScAef ceR/M7AP4kLP/PjDCYKjb98hV7xYlzqqeXqyHmlAU4tsht+id5F2zzhw+/A6FuFU0OTy MQQgpH6yZruzxncfSequRGMtWDbBTglcwesAGyxsGKCzX6zSVGhct0h3X2G1OrsnE6vC IxN6ckpLC6Uy2wlZVeLY7xafATu4jXq0lZ53iiRMaGCnHgQFqk8NT3crT/Xu1X5UW0Em S9pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=VbHSe5ZmokTeRZOVR5/DxbeDukJUOZWqPm1zkRBz3bc=; b=sBGJ9/kBP1F/AreucvOoXqlQMUs33CPeWfp00CNi4j9kznNEMVvmcoXgOF2UtylZlj RfrborwDXEFypNltOqqiwGC2vyTvDq7PcDw1bmPEAF7W5EaFl8dhP/BJK36H3tduHpV3 OAlI9e+ly2b9nk4O51jFObzAvedXklYzKSxParxhO6bYITZ1FFV7vEKN4wkn4fNXu57S aoO+tbhArAP0rHD1sivKrQscdmJHuLETjszMBT1vIhd53C3uAW0aO0PznErGQJ0TquXJ mw5TRAp9tCux2m98nZSxRYf9hmCEm+VcCs5SzJwkAO3kBEsHMU+3mxmMSuLOJUn04zPR 0KSA== X-Gm-Message-State: AOAM532RNt0GXrLYM1nW+m+Vi0sRs7lWzYIS8l4eGGWFCFQHfIlgbxm/ 7TKlH45uEqvW9BnaR+cd7EabQPXCSW2H2KNNWp0= X-Received: by 2002:a05:6512:3148:: with SMTP id s8mr341209lfi.513.1627490475453; Wed, 28 Jul 2021 09:41:15 -0700 (PDT) MIME-Version: 1.0 References: <20210722054159.4459-1-lingshan.zhu@intel.com> In-Reply-To: From: Like Xu Date: Thu, 29 Jul 2021 00:40:59 +0800 Message-ID: Subject: Re: [PATCH V9 00/18] KVM: x86/pmu: Add *basic* support to enable guest PEBS via DS To: Peter Zijlstra , Paolo Bonzini Cc: Zhu Lingshan , Borislav Petkov , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , "Liang, Kan" , ak@linux.intel.com, wei.w.wang@intel.com, Stephane Eranian , Liuxiangdong , linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org, boris.ostrvsky@oracle.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 28, 2021 at 11:46 PM Peter Zijlstra wrote: > > On Thu, Jul 22, 2021 at 01:41:41PM +0800, Zhu Lingshan wrote: > > The guest Precise Event Based Sampling (PEBS) feature can provide an > > architectural state of the instruction executed after the guest instruction > > that exactly caused the event. It needs new hardware facility only available > > on Intel Ice Lake Server platforms. This patch set enables the basic PEBS > > feature for KVM guests on ICX. > > > > We can use PEBS feature on the Linux guest like native: > > > > # echo 0 > /proc/sys/kernel/watchdog (on the host) > > # perf record -e instructions:ppp ./br_instr a > > # perf record -c 100000 -e instructions:pp ./br_instr a > > Why does the host need to disable the watchdog? IIRC ICL has multiple > PEBS capable counters. Also, I think the watchdog ends up on a fixed > counter by default anyway. The watchdog counter blocks the KVM PEBS request on the same (fixed) counter. This restriction will be lifted when we have cross-mapping support later in KVM. > > > Like Xu (17): > > perf/core: Use static_call to optimize perf_guest_info_callbacks > > perf/x86/intel: Add EPT-Friendly PEBS for Ice Lake Server > > perf/x86/intel: Handle guest PEBS overflow PMI for KVM guest > > perf/x86/core: Pass "struct kvm_pmu *" to determine the guest values > > KVM: x86/pmu: Set MSR_IA32_MISC_ENABLE_EMON bit when vPMU is enabled > > KVM: x86/pmu: Introduce the ctrl_mask value for fixed counter > > KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS > > KVM: x86/pmu: Reprogram PEBS event to emulate guest PEBS counter > > KVM: x86/pmu: Adjust precise_ip to emulate Ice Lake guest PDIR counter > > KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to support guest DS > > KVM: x86/pmu: Add PEBS_DATA_CFG MSR emulation to support adaptive PEBS > > KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled > > KVM: x86/pmu: Move pmc_speculative_in_use() to arch/x86/kvm/pmu.h > > KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations > > KVM: x86/pmu: Add kvm_pmu_cap to optimize perf_get_x86_pmu_capability > > KVM: x86/cpuid: Refactor host/guest CPU model consistency check > > KVM: x86/pmu: Expose CPUIDs feature bits PDCM, DS, DTES64 > > > > Peter Zijlstra (Intel) (1): > > x86/perf/core: Add pebs_capable to store valid PEBS_COUNTER_MASK value > > Looks good: > > Acked-by: Peter Zijlstra (Intel) Thanks for your time and support of the guest PMU features. > How do we want to route this, all through the KVM tree? As a prerequisite, the perf tree may apply the first three patches. Hi Paolo, do you have any preferences ? > > One little nit I had; would something like the below (on top perhaps) > make the code easier to read? Fine to me and I may provide a follow-up patch. > > --- > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -3921,9 +3921,12 @@ static struct perf_guest_switch_msr *int > struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data; > u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl); > u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable; > + int global_ctrl, pebs_enable; > > *nr = 0; > - arr[(*nr)++] = (struct perf_guest_switch_msr){ > + > + global_ctrl = (*nr)++; > + arr[global_ctrl] = (struct perf_guest_switch_msr){ > .msr = MSR_CORE_PERF_GLOBAL_CTRL, > .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask, > .guest = intel_ctrl & (~cpuc->intel_ctrl_host_mask | ~pebs_mask), > @@ -3966,23 +3969,23 @@ static struct perf_guest_switch_msr *int > }; > } > > - arr[*nr] = (struct perf_guest_switch_msr){ > + pebs_enable = (*nr)++; > + arr[pebs_enable] = (struct perf_guest_switch_msr){ > .msr = MSR_IA32_PEBS_ENABLE, > .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask, > .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask, > }; > > - if (arr[*nr].host) { > + if (arr[pebs_enable].host) { > /* Disable guest PEBS if host PEBS is enabled. */ > - arr[*nr].guest = 0; > + arr[pebs_enable].guest = 0; > } else { > /* Disable guest PEBS for cross-mapped PEBS counters. */ > - arr[*nr].guest &= ~kvm_pmu->host_cross_mapped_mask; > + arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; > /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ > - arr[0].guest |= arr[*nr].guest; > + arr[global_ctrl].guest |= arr[pebs_enable].guest; > } > > - ++(*nr); > return arr; > } > > > >