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Date:   Wed, 28 Jul 2021 21:47:42 +0300
From:   Vladimir Oltean <olteanv@gmail.com>
To:     DENG Qingfang <dqfext@gmail.com>
Cc:     Sean Wang <sean.wang@mediatek.com>,
        Landen Chao <Landen.Chao@mediatek.com>,
        Andrew Lunn <andrew@lunn.ch>,
        Vivien Didelot <vivien.didelot@gmail.com>,
        Florian Fainelli <f.fainelli@gmail.com>,
        "David S. Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [RFC net-next 2/2] net: dsa: mt7530: trap packets from
 standalone ports to the CPU
Message-ID: <20210728184742.cyoh7ucvxwlbdpnu@skbuf>
References: <20210728175327.1150120-1-dqfext@gmail.com>
 <20210728175327.1150120-3-dqfext@gmail.com>
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In-Reply-To: <20210728175327.1150120-3-dqfext@gmail.com>
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On Thu, Jul 29, 2021 at 01:53:26AM +0800, DENG Qingfang wrote:
>  /* Register for setup vlan and acl write data */
> @@ -153,6 +162,35 @@ enum mt7530_vlan_cmd {
>  #define  PORT_MEM_SHFT			16
>  #define  PORT_MEM_MASK			0xff
>  
> +/* ACL rule pattern */
> +#define  BIT_CMP(x)			(((x) & 0xffff) << 16)
> +#define  CMP_PAT(x)			((x) & 0xffff)

not used

> +
> +/* ACL rule action */
> +#define  ACL_MANG			BIT(29)
> +#define  ACL_INT_EN			BIT(28)
> +#define  ACL_CNT_EN			BIT(27)
> +#define  ACL_CNT_IDX(x)			(((x) & 0x7) << 24)
> +#define  VLAN_PORT_EN			BIT(23)
> +#define  DA_SWAP			BIT(22)
> +#define  SA_SWAP			BIT(21)
> +#define  PPP_RM				BIT(20)
> +#define  LKY_VLAN			BIT(19)
> +#define  ACL_EG_TAG(x)			(((x) & 0x7) << 16)
> +#define  ACL_PORT(x)			(((x) & 0xff) << 8)
> +#define  ACL_PORT_EN			BIT(7)
> +#define  PRI_USER(x)			(((x) & 0x7) << 4)
> +#define  ACL_MIR_EN			BIT(3)
> +#define  ACL_PORT_FW(x)			((x) & 0x7)
> +
> +enum mt7530_to_cpu_port_fw {
> +	PORT_FW_DEFAULT,
> +	PORT_FW_EXCLUDE_CPU = 4,
> +	PORT_FW_INCLUDE_CPU,
> +	PORT_FW_CPU_ONLY,
> +	PORT_FW_DROP,
> +};

not used

> +
>  #define MT7530_VAWD2			0x98
>  /* Egress Tag Control */
>  #define  ETAG_CTRL_P(p, x)		(((x) & 0x3) << ((p) << 1))
> @@ -164,6 +202,23 @@ enum mt7530_vlan_egress_attr {
>  	MT7530_VLAN_EGRESS_STACK = 3,
>  };
>  
> +/* ACL rule pattern */
> +#define  ACL_TABLE_EN			BIT(19)
> +#define  OFST_TP(x)			(((x) & 0x7) << 16)
> +#define  ACL_SP(x)			(((x) & 0xff) << 8)
> +#define  WORD_OFST(x)			(((x) & 0x7f) << 1)
> +#define  CMP_SEL			BIT(0)

not used

> +
> +enum mt7530_acl_offset_type {
> +	MT7530_ACL_MAC_HEADER,
> +	MT7530_ACL_L2_PAYLOAD,
> +	MT7530_ACL_IP_HEADER,
> +	MT7530_ACL_IP_DATAGRAM,
> +	MT7530_ACL_TCP_UDP_HEADER,
> +	MT7530_ACL_TCP_UDP_DATAGRAM,
> +	MT7530_ACL_IPV6_HEADER,
> +};

not used

> +
>  /* Register for address age control */
>  #define MT7530_AAC			0xa0
>  /* Disable ageing */
> @@ -192,6 +247,7 @@ enum mt7530_stp_state {
>  
>  /* Register for port control */
>  #define MT7530_PCR_P(x)			(0x2004 + ((x) * 0x100))
> +#define  PORT_ACL_EN			BIT(10)
>  #define  PORT_TX_MIR			BIT(9)
>  #define  PORT_RX_MIR			BIT(8)
>  #define  PORT_VLAN(x)			((x) & 0x3)
> -- 
> 2.25.1
>