Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp5559906pxv; Wed, 28 Jul 2021 13:43:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyotjCXBnc1wsltBw8aEnY0+TtOORWgFKXaWmb+d0x+Dqk9XDRAvTIgQTeNpniXdzYvDB9H X-Received: by 2002:a92:d783:: with SMTP id d3mr1016680iln.193.1627505036679; Wed, 28 Jul 2021 13:43:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627505036; cv=none; d=google.com; s=arc-20160816; b=OXJUhILvff3ggC8vbXWCZGAdUOh/Tg3/WQcNN9Q5P/UifxTE4D9w2Q1ATDZIsqw9aZ bY1emH4SA7hDnS+0jgsgKFbXAtIPFrh/1TNjb3GMFQiWHRDbcTZE9kvJBT5fRKVJqyNq o6KEedVrjsf5ToQhJyJLrn5V+rQAU2AEBRFnKGr9fRKGXcYKRJ6Xd4OdVE2dQVKnfqQn BZDMrRcdUl/Tb44iy4YY4B3cuaBMX+oSQWcj0d5Q3KmyVDZCHIXylIZx92Nh5Doc0WTn aSAVoKplSC6Pbqs/KHqJDwOOhtnuZuFnJHaBloeW1tn9tWt5aCWQN6cYdxt3Ai/ntTIk FU/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=R7bNU8BZCOB5iHa54MHFRtshuOZCZQe5szk1h/9GSv4=; b=dLkhDnMljF5UE4erdCrUFIH+e6EZRvKn5v91WMvP5nvKDCVg0OTekd1kKjSHQiq5Xo dHKEQSNsIE8OS7gsB9Ogd6qF93dcCkxhFfz+3/wCbprwBWz9YaP1qjz2jNTMxHYyeF84 f3xN/aKIn6qGw/8/T3MW41L2OBwx00UmVp8qCX18zjUQc6rIcJabnjj4G2g3nJtQXpX8 ZCY48VdCBZ276XjOvWnGNwPIob+WsRb0JmJHSNat3a6K+EiIwqBj2P1YLPqiPjWQRsED jqqXEKFR9F7gTV0DH/hgodYdPGaStt4+wV2gZolO3hY+I0tUSeyEqeBEewAB/o2+H6y+ 5XUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b=J3gS7vLV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e16si921736ils.75.2021.07.28.13.43.44; Wed, 28 Jul 2021 13:43:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b=J3gS7vLV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231668AbhG1UiA (ORCPT + 99 others); Wed, 28 Jul 2021 16:38:00 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:50656 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231571AbhG1Uh7 (ORCPT ); Wed, 28 Jul 2021 16:37:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=R7bNU8BZCOB5iHa54MHFRtshuOZCZQe5szk1h/9GSv4=; b=J3gS7vLVbdobYkuyQnS/5NIZXG LM0+y/ogncES/luhSa1aiof9fn2vigm1e0bj6MkI7gkilPMaCrc89un0I56HZ6f6UEBkvBSvGDbo/ CXREAGn3PQPnFRYRnNDDhBsDf9GKxjETl0hHhOkDzzVIfEy1XHZJptJ7qwL74WvfnaN4=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1m8qJK-00FEMI-Rg; Wed, 28 Jul 2021 22:37:50 +0200 Date: Wed, 28 Jul 2021 22:37:50 +0200 From: Andrew Lunn To: Peter Geis Cc: Michael Riesch , devicetree@vger.kernel.org, arm-mail-list , "open list:ARM/Rockchip SoC..." , Linux Kernel Mailing List , Rob Herring , Heiko Stuebner , Liang Chen , Simon Xue Subject: Re: [PATCH 2/2] arm64: dts: rockchip: rk3568-evb1-v10: add ethernet support Message-ID: References: <20210728161020.3905-1-michael.riesch@wolfvision.net> <20210728161020.3905-3-michael.riesch@wolfvision.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Generally all rockchip boards use this value instead of the rgmii_id, > I imagine because it's more consistent to tune here than the hit or > miss support of the phy drivers. Most PHY drivers actually implement it correctly, since by default, most systems get the PHY to do the delays. But if most Rockchip boards do it this way, there is a lot to be said for consistence, so this is fine by me. Andrew