Received: by 2002:a05:6a10:1287:0:0:0:0 with SMTP id d7csp5709519pxv; Wed, 28 Jul 2021 18:15:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyhdckmVD0npbdFCvj5/NqT/ACkC2VNjSbMXdHvvOHcH3ubLElfRyTB2fbAnPsmbWRa8yIl X-Received: by 2002:a92:c748:: with SMTP id y8mr1856805ilp.2.1627521320297; Wed, 28 Jul 2021 18:15:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627521320; cv=none; d=google.com; s=arc-20160816; b=LjjcdeY2mG8yt5wi95dgWw8SggQ1LpeESdDrcFlCj7/hMNrxurGPPDjj9BGgJiN8kt cTuCxvb41+gH0z89imNi6N/1pIbzQk7qKSHRTSR/Qpt1AX0PEb4TR1IS1ujDp8I87YYJ MHFSmBJH+NaK6Kehe1gSSjtMpwtIzvwT8yFEuwgRG6fqCbabju1eE76nvJwnDehmqIDV Z4JQYOM5xH6pIaEHUhOvpoDAv4reKGdpdjI20kOKmA+RrC211gRd90JPfwndjHVNgleN ykISK2M50vbiTbeRAtiqm1q+E0gTj4Car0nym/Bi4mTdsMJalY3mjHMVk0bDoitDFMn+ nBmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=w3eqHGMGnZrc4/+v+wtfBYqAmtbWxOwgb0eJIVdMEG0=; b=bOwWdBI+meNmDGb1/oVoCq60ZxQTxWPSKmANXLLqoPLJUG8j1fhg5NnuDjSa9/Ls5u JRsoneFwI7Gt0FiDhkv124vX9nQX9ALFu0yr/I37kTuSUSnoVK3tcS5tv1p8XjLD/vK/ FWDHVIWarjCr16vflmKgf1sl/kmA3s9oD8KBIMdoO096AVmrgCD1vSiJrs0IBof10X5i lClOGhojmAKNkIV+c1JVHBLgskvw0cuFlmGvdtpJ0yw30z9el+XDU03UsYz5tOVASJKG eyOaVfVBYX4SfKVShfB2W98PuNQFe8UWoiZ4kYZ2MPh+SLnKMohaaV3ZfaEzP8HSnAqG urHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@quicinc.com header.s=qcdkim header.b=eQLalI92; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y11si2063794ilu.1.2021.07.28.18.15.09; Wed, 28 Jul 2021 18:15:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=fail header.i=@quicinc.com header.s=qcdkim header.b=eQLalI92; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233270AbhG2BNy (ORCPT + 99 others); Wed, 28 Jul 2021 21:13:54 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:18606 "EHLO alexa-out-sd-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233244AbhG2BNt (ORCPT ); Wed, 28 Jul 2021 21:13:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1627521226; x=1659057226; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Q9cKJpllo1DhhME1a3XXJiNfVwTF4UKgzs2i3F4Z3Zw=; b=eQLalI927FBLDTfGHF/+tq/NIXp6/fPawZtW3vTRyOueQW6tjs5fZs8w JK8uaBnDK/Ww6gktLZP0xDPDJZXZxuzft++Edg66JGoUMJyi3C9C0yArW iOIFh6cIDtByPvvkxQ37xH0vJx8KlwtfwYigSH/3egIM8W0IXZZLcynfE Y=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 28 Jul 2021 18:13:46 -0700 X-QCInternal: smtphost Received: from nasanexm03e.na.qualcomm.com ([10.85.0.48]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/AES256-SHA; 28 Jul 2021 18:13:46 -0700 Received: from fenglinw-gv.qualcomm.com (10.80.80.8) by nasanexm03e.na.qualcomm.com (10.85.0.48) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Wed, 28 Jul 2021 18:13:44 -0700 From: Fenglin Wu To: , , CC: , , Subject: [PATCH V1 2/9] spmi: pmic-arb: do not ack and clear peripheral interrupts in cleanup_irq Date: Thu, 29 Jul 2021 09:12:40 +0800 Message-ID: <1627521167-18848-3-git-send-email-quic_fenglinw@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1627521167-18848-1-git-send-email-quic_fenglinw@quicinc.com> References: <1627521167-18848-1-git-send-email-quic_fenglinw@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanexm03e.na.qualcomm.com (10.85.0.48) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Subbaraman Narayanamurthy Currently, cleanup_irq() is invoked when a peripheral's interrupt fires and there is no mapping present in the interrupt domain of spmi interrupt controller. The cleanup_irq clears the arbiter bit, clears the pmic interrupt and disables it at the pmic in that order. The last disable in cleanup_irq races with request_irq() in that it stomps over the enable issued by request_irq. Fix this by not writing to the pmic in cleanup_irq. The latched bit will be left set in the pmic, which will not send us more interrupts even if the enable bit stays enabled. When a client wants to request an interrupt, use the activate callback on the irq_domain to clear latched bit. This ensures that the latched, if set due to the above changes in cleanup_irq or when the bootloader leaves it set, gets cleaned up, paving way for upcoming interrupts to trigger. With this, there is a possibility of unwanted triggering of interrupt right after the latched bit is cleared - the interrupt may be left enabled too. To avoid that, clear the enable first followed by clearing the latched bit in the activate callback. Signed-off-by: Subbaraman Narayanamurthy [collinsd@codeaurora.org: fix merge conflict] Signed-off-by: David Collins Signed-off-by: Fenglin Wu --- drivers/spmi/spmi-pmic-arb.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 295e19f..4d7ad004 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -492,16 +492,6 @@ static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n", __func__, apid, sid, per, id); writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); - - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); - - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid, - (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1)) - dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n", - irq_mask, ppid); } static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) @@ -667,6 +657,7 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain, u16 apid = hwirq_to_apid(d->hwirq); u16 sid = hwirq_to_sid(d->hwirq); u16 irq = hwirq_to_irq(d->hwirq); + u8 buf; if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) { dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n", @@ -675,6 +666,10 @@ static int qpnpint_irq_domain_activate(struct irq_domain *domain, return -ENODEV; } + buf = BIT(irq); + qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1); + qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1); + return 0; } -- Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.