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From:   Rob Herring <robh@kernel.org>
Date:   Thu, 29 Jul 2021 08:50:10 -0600
Message-ID: <CAL_JsqLhxGFV9iBhbYj7QNct54Se7pBhhTgFyqRYO0uLvoPnmg@mail.gmail.com>
Subject: Re: [PATCH 3/5] dt-bindings: PCI: kirin: Add support for Kirin970
To:     Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Cc:     Linuxarm <linuxarm@huawei.com>, mauro.chehab@huawei.com,
        Binghui Wang <wangbinghui@hisilicon.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Xiaowei Song <songxiaowei@hisilicon.com>,
        devicetree@vger.kernel.org,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        PCI <linux-pci@vger.kernel.org>
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On Thu, Jul 29, 2021 at 5:56 AM Mauro Carvalho Chehab
<mchehab+huawei@kernel.org> wrote:
>
> Add a new compatible, plus the new bindings needed by
> HiKey970 board.
>
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
> ---
>  .../bindings/pci/hisilicon,kirin-pcie.yaml    | 61 ++++++++++++++++++-
>  1 file changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> index 90cab09e8d4b..bb0c3a081d68 100644
> --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
> @@ -24,11 +24,13 @@ properties:
>      contains:
>        enum:
>          - hisilicon,kirin960-pcie
> +        - hisilicon,kirin970-pcie
>
>    reg:
>      description: |
>        Should contain dbi, apb, config registers location and length.
> -      For HiKey960, it should also contain phy.
> +      For HiKey960, it should also contain phy. All other devices
> +      should use a separate phy driver.
>      minItems: 3
>      maxItems: 4
>
> @@ -47,6 +49,7 @@ examples:
>    - |
>      #include <dt-bindings/interrupt-controller/arm-gic.h>
>      #include <dt-bindings/clock/hi3660-clock.h>
> +    #include <dt-bindings/clock/hi3670-clock.h>
>
>      soc {
>        #address-cells = <2>;
> @@ -83,4 +86,60 @@ examples:
>          clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
>                        "pcie_apb_sys", "pcie_aclk";
>        };
> +
> +      pcie@f5000000 {
> +        compatible = "hisilicon,kirin970-pcie";
> +        reg = <0x0 0xf4000000 0x0 0x1000000>,
> +              <0x0 0xfc180000 0x0 0x1000>,
> +              <0x0 0xf5000000 0x0 0x2000>;
> +        reg-names = "dbi", "apb", "config";
> +        bus-range = <0x0  0x1>;
> +        msi-parent = <&its_pcie>;
> +        #address-cells = <3>;
> +        #size-cells = <2>;
> +        device_type = "pci";
> +        phys = <&pcie_phy>;
> +        ranges = <0x02000000 0x0 0x00000000
> +                  0x0 0xf6000000
> +                  0x0 0x02000000>;
> +        num-lanes = <1>;
> +        #interrupt-cells = <1>;
> +        interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-names = "msi";
> +        interrupt-map-mask = <0 0 0 7>;
> +        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> +                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> +                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> +                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> +        pcie@4,0 { // Lane 4: M.2

You are missing a level here. You need the upstream bridge device. I
figured this out for you, why am I having to correct it?

Isn't this supposed to be Device 1 as 1 and 4 are swapped in terms of
lane number and device number.

> +          reg = <0 0 0 0 0>;

Not the right address. I would have expected a dtc warning on this.

> +          compatible = "pciclass,0604";
> +          device_type = "pci";
> +          reset-gpios = <&gpio7 1 0>;
> +          clkreq-gpios = <&gpio27 3 0 >;
> +          #address-cells = <3>;
> +          #size-cells = <2>;
> +          ranges;
> +        };
> +        pcie@5,0 { // Lane 5: Mini PCIe

It's device 5 not lane 5.


> +          reg = <0 0 0 0 0>;
> +          compatible = "pciclass,0604";
> +          device_type = "pci";
> +          reset-gpios = <&gpio7 2 0>;
> +          clkreq-gpios = <&gpio17 0 0 >;
> +          #address-cells = <3>;
> +          #size-cells = <2>;
> +          ranges;
> +        };
> +        pcie@7,0 { // Lane 7: Ethernet
> +          reg = <0 0 0 0 0>;
> +          compatible = "pciclass,0604";
> +          device_type = "pci";
> +          reset-gpios = <&gpio7 3 0>;
> +          clkreq-gpios = <&gpio20 0 0 >;
> +          #address-cells = <3>;
> +          #size-cells = <2>;
> +          ranges;
> +        };
> +      };
>      };
> --
> 2.31.1
>