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From:   "Joshi, Mukul" <Mukul.Joshi@amd.com>
To:     "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
CC:     Borislav Petkov <bp@alien8.de>,
        Alex Deucher <alexdeucher@gmail.com>, x86-ml <x86@kernel.org>,
        "Kasiviswanathan, Harish" <Harish.Kasiviswanathan@amd.com>,
        lkml <linux-kernel@vger.kernel.org>,
        "amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>
Subject: RE: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran
Thread-Topic: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran
Thread-Index: AQHXRs6Uco2r7eCCPEW3XTp7lQLNb6rflw+AgACR7NCAAC6FAIAAV7jwgAB+vQCAAEnsgIAAA5mAgAAAloCAAAbygIAAie6ggACEBQCAFURmoIALF48AgFgrUTA=
Date:   Thu, 29 Jul 2021 23:59:43 +0000
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[AMD Official Use Only]


> -----Original Message-----
> From: Ghannam, Yazen <Yazen.Ghannam@amd.com>
> Sent: Thursday, June 3, 2021 5:13 PM
> To: Joshi, Mukul <Mukul.Joshi@amd.com>
> Cc: Borislav Petkov <bp@alien8.de>; Alex Deucher <alexdeucher@gmail.com>;
> x86-ml <x86@kernel.org>; Kasiviswanathan, Harish
> <Harish.Kasiviswanathan@amd.com>; lkml <linux-kernel@vger.kernel.org>;
> amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran
>=20
> On Thu, May 27, 2021 at 03:54:27PM -0400, Joshi, Mukul wrote:
> ...
> > > Is that the same deferred interrupt which calls
> > > amd_deferred_error_interrupt() ?
> >
> > Sorry picking this up after sometime. I thought I had replied to this e=
mail.
> > Yes it is the same deferred interrupt which calls
> amd_deferred_error_interrupt().
> >
>=20
> Mukul,
>=20
> Do you expect that the driver will need to mark pages with high correctab=
le
> error counts as bad? I think the hardware folks may want the GPU memory
> errors to be handled more aggressively than CPU memory errors. The specif=
ic
> threshold may change from product to product, so it may make sense to
> hardcode this in the driver.
>=20

Sorry I missed this email completely. Just saw it so responding now.

At the moment, we don't have a requirement to mark a page "bad" if there is=
 a high correctable error counts.=20
Our previous GPU ASICs which support RAS, also do not have such a feature.
But you make a good point. It might be worthwhile to go and ask the hardwar=
e folks about it.

> We have similar functionality in the Correctable Errors Collector. But en=
terprise
> users may prefer a direct approach done in the driver (based on the hardw=
are
> experts' guidance) instead of configuring the kernel at runtime.
>=20
> So I think having a separate priority may make sense if some special
> functionality, or combination of behaviors, is needed which don't fall un=
der any
> exisiting things. In this case, "special functionality" could be that the=
 GPU
> memory needs to be handled differently than CPU memory.
>=20
> Another thing is that this behavior is similar to the NFIT behavior, i.e.=
 there's a
> memory error on an external device that needs to be handled by the device=
's
> driver. So maybe we can rename MCE_PRIO_NFIT to be generic
> (MCE_PRIO_EXTERNAL?) and use that? Multiple notifiers with the same prior=
ity
> is okay, right?
>=20
With respect to MCE priority, I was thinking of using the MCE_PRIO_EDAC ins=
tead of creating a new priority as the code in the GPU driver is doing erro=
r detection and handling the uncorrectable errors.
Not sure if that aligns with the definition of EDAC device in the kernel.

What do you think?

Regards,
Mukul

> Thanks,
> Yazen