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Fri, 30 Jul 2021 10:43:23 +0800 Message-ID: Subject: Re: [v6 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 From: Chun-Jie Chen To: Ikjoon Jang CC: Matthias Brugger , Rob Herring , Nicolas Boichat , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/Mediatek SoC support" , open list , "moderated list:ARM/Mediatek SoC support" , srv_heupstream , Project_Global_Chrome_Upstream_Group Date: Fri, 30 Jul 2021 10:43:23 +0800 In-Reply-To: References: <20210727023205.20319-1-chun-jie.chen@mediatek.com> <20210727023205.20319-3-chun-jie.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org T24gV2VkLCAyMDIxLTA3LTI4IGF0IDE0OjE0ICswODAwLCBJa2pvb24gSmFuZyB3cm90ZToNCj4g SGksDQo+IA0KPiBPbiBUdWUsIEp1bCAyNywgMjAyMSBhdCAxMDo0MyBBTSBDaHVuLUppZSBDaGVu DQo+IDxjaHVuLWppZS5jaGVuQG1lZGlhdGVrLmNvbT4gd3JvdGU6DQo+ID4gDQo+ID4gaW5mcmFf dWFydDAgY2xvY2sgaXMgdGhlIHJlYWwgb25lIHdoYXQgdWFydDAgdXNlcyBhcyBidXMgY2xvY2su DQo+ID4gDQo+ID4gU2lnbmVkLW9mZi1ieTogV2VpeWkgTHUgPHdlaXlpLmx1QG1lZGlhdGVrLmNv bT4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBDaHVuLUppZSBDaGVuIDxjaHVuLWppZS5jaGVuQG1lZGlh dGVrLmNvbT4NCj4gPiAtLS0NCj4gPiAgYXJjaC9hcm02NC9ib290L2R0cy9tZWRpYXRlay9tdDgx OTIuZHRzaSB8IDIgKy0NCj4gPiAgMSBmaWxlIGNoYW5nZWQsIDEgaW5zZXJ0aW9uKCspLCAxIGRl bGV0aW9uKC0pDQo+ID4gDQo+ID4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQvYm9vdC9kdHMvbWVk aWF0ZWsvbXQ4MTkyLmR0c2kNCj4gPiBiL2FyY2gvYXJtNjQvYm9vdC9kdHMvbWVkaWF0ZWsvbXQ4 MTkyLmR0c2kNCj4gPiBpbmRleCBjN2M3ZDRlMDE3YWUuLjk4MTBmMWQ0NDFkYSAxMDA2NDQNCj4g PiAtLS0gYS9hcmNoL2FybTY0L2Jvb3QvZHRzL21lZGlhdGVrL210ODE5Mi5kdHNpDQo+ID4gKysr IGIvYXJjaC9hcm02NC9ib290L2R0cy9tZWRpYXRlay9tdDgxOTIuZHRzaQ0KPiA+IEBAIC0zMjcs NyArMzI3LDcgQEANCj4gPiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIm1l ZGlhdGVrLG10NjU3Ny11YXJ0IjsNCj4gPiAgICAgICAgICAgICAgICAgICAgICAgICByZWcgPSA8 MCAweDExMDAyMDAwIDAgMHgxMDAwPjsNCj4gPiAgICAgICAgICAgICAgICAgICAgICAgICBpbnRl cnJ1cHRzID0gPEdJQ19TUEkgMTA5DQo+ID4gSVJRX1RZUEVfTEVWRUxfSElHSCAwPjsNCj4gPiAt ICAgICAgICAgICAgICAgICAgICAgICBjbG9ja3MgPSA8JmNsazI2bT4sIDwmY2xrMjZtPjsNCj4g PiArICAgICAgICAgICAgICAgICAgICAgICBjbG9ja3MgPSA8JmNsazI2bT4sIDwmaW5mcmFjZmcN Cj4gPiBDTEtfSU5GUkFfVUFSVDA+Ow0KPiA+ICAgICAgICAgICAgICAgICAgICAgICAgIGNsb2Nr LW5hbWVzID0gImJhdWQiLCAiYnVzIjsNCj4gPiAgICAgICAgICAgICAgICAgICAgICAgICBzdGF0 dXMgPSAiZGlzYWJsZWQiOw0KPiA+ICAgICAgICAgICAgICAgICB9Ow0KPiANCj4gVGhlcmUncmUg bWFueSBvdGhlciBub2RlcyBzdGlsbCBoYXZpbmcgb25seSBjbGsyNm0uIFdpbGwgeW91IHVwZGF0 ZQ0KPiB0aGVtIHRvbz8NCj4gDQoNCk90aGVycyB3aWxsIGJlIHVwZGF0ZWQgYnkgSVAgb3duZXIu DQoNCkJlc3QgUmVnYXJkcywNCkNodW4tSmllDQoNCj4gPiAtLQ0KPiA+IDIuMTguMA0KPiA+IF9f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fDQo+ID4gTGludXgt bWVkaWF0ZWsgbWFpbGluZyBsaXN0DQo+ID4gTGludXgtbWVkaWF0ZWtAbGlzdHMuaW5mcmFkZWFk Lm9yZw0KPiA+IA0KaHR0cHM6Ly91cmxkZWZlbnNlLmNvbS92My9fX2h0dHA6Ly9saXN0cy5pbmZy YWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtbWVkaWF0ZWtfXzshIUNUUk5LQTl3TWcw QVJidyExYkl6NlgyRWlGYmlnQ0ltelFtYnF0ZXpJRmZsMUxSQnVQT1lUcUJkbDV3Zng4Yi16cDB6 UVA2OFI3UmhhSWNBQVhYRiQNCj4gPiAgDQo=